Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach

  • Andreas Raptopoulos
  • Sotirios Xydis
  • Dimitrios Soudris
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9040)

Abstract

This paper presents the main directions of the AEGLE project, that targets to integrate cloud technologies together with heterogeneous reconfigurable computing in large scale healthcare systems for Big Bio-Data analytics. AEGLE’s concept brings together the ’hot’ big-data technologies with the health ’industry’ eventually leading to integrated care and creating a win-win situation for both. We provide the addressed Big Data health scenarios and we describe the structural elements of the proposed solution, with emphasis given in the exploitation of high-performance reconfigurable engines for Big Data analytics acceleration integrated to the AEGLE ecosystem, enabling personalized and integrated health-care services, while also promoting related research activities.

Keywords

Chronic Lymphocytic Leukemia MapReduce Framework Reconfigurable Computing Analytics Acceleration Related Research Activity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Transforming health care through big data, Institute for Health Technology Information. http://www.ihealthtran.com/big_data_in_healthcare.html
  2. 2.
  3. 3.
  4. 4.
  5. 5.
    Barrett, T., Wilhite, S.E., Ledoux, P., et al.: NCBI GEO: archive for functional genomics data sets update. Nucl. Acids Res. 41(D1), D991–D995 (2013)Google Scholar
  6. 6.
    Kodama, Y., Shumway, M., et al.: The sequence read archive: explosive growth of sequencing data. Nucl. Acids Res. 40(D1), D54–D56 (2012)CrossRefGoogle Scholar
  7. 7.
    National Institute for Health and Care Excellence. Preventing type 2 diabetes: risk identification and interventions for individuals at high risk. NICE public health guidance 38 (2012). http://www.guidance.nice.org.uk/ph38
  8. 8.
    Maxeler Technologies. http://www.maxeler.com
  9. 9.
    Dean, J., Ghemawat, S.: MapReduce: simplified data processing on large clusters. In: Proc. Sixth Symp. on Operating System Design and Implementation (OSDI 2004), pp. 137–150 (2004)Google Scholar
  10. 10.
    Apache Hadoop. http://hadoop.apache.org
  11. 11.
    Grund, M., Kruger, J., Plattner, H., Zeier, A., Cudre-Mauroux, P., Madden, S.: HYRISE - a main memory hybrid storage engine. In: VLDB (2012)Google Scholar
  12. 12.
    Stonebraker, M., et al.: The end of an architectural era (its time for a complete rewrite). In: VLDB (2007)Google Scholar
  13. 13.
    Raman, V., Attaluri, G., Barber, R., Chainani, N., Kalmuk, D., KulandaiSamy, V., Leenstra, J., Lightstone, S., Liu, S., Lohman, G.M., Malkemus, T., Mueller, R., Pandis, I., Schiefer, B., Sharpe, D., Sidle, R., Storm, A., Zhang, L.: DB2 with BLU acceleration: so much more than just a column store. Proc. VLDB Endow. 6, 11, 1080–1091 (2013)Google Scholar
  14. 14.
    Shan, Y., Wang, B., Yan, J., Wang, Y., Xu, N., Yang, H.: FPMR: mapReduce framework on FPGA. In: Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010)Google Scholar
  15. 15.
    Xydis, S., Bartzas, A., Anagnostopoulos, I., Soudris, D., Pekmestzi, K.: Custom multi-threaded dynamic memory management for multiprocessor system-on-chip platforms. In: 2010 International Conference on Embedded Computer Systems (SAMOS), July 19–22, pp. 102–109 (2010)Google Scholar
  16. 16.
    Anagnostopoulos, I., Xydis, S., Bartzas, A., Zhonghai, L., Soudris, D., Jantsch, A.: Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations. IEEE Embedded Systems Letters 3(2), 66–69 (2011)CrossRefGoogle Scholar
  17. 17.
    Xydis, S., Stamelakos, I., Bartzas, A., Soudris, D.: Runtime tuning of dynamic memory management for mitigating footprint-fragmentation variations. In: Proc. of PARMA Workshop, pp. 27–36. VDE Verlang (2011)Google Scholar
  18. 18.
    Diamantopoulos, D., Xydis, S., Siozios, K., Soudris, D.: Dynamic memory management in vivado-hls for scalable many-accelerator architectures. In: Sano, K. (ed.) ARC 2015. LNCS, pp. XX–YY. Springer, Heidelberg (2015)Google Scholar
  19. 19.
    Xydis, S., Palermo, G., Zaccaria, V., Silvano, C.: SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34(1), 155–159 (2015)CrossRefGoogle Scholar
  20. 20.
    Xydis, S., Pekmestzi, K., Soudris, D., Economakos, G.: Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. ACM Trans. Des. Autom. Electron. Syst. 18(1), Article 11, 35 pages (2013)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Andreas Raptopoulos
    • 1
  • Sotirios Xydis
    • 2
  • Dimitrios Soudris
    • 2
  1. 1.EXUSAthensGreece
  2. 2.School of Electrical and Computer EngineeringNational Technical University of AthensAthensGreece

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