Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects

  • Lucas A. TambaraEmail author
  • Felipe Almeida
  • Paolo Rech
  • Fernanda L. Kastensmidt
  • Giovanni Bruni
  • Christopher Frost
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9040)


TMR is the most widely used technique to increase the reliability of SRAM-based FPGAs used in safety-critical applications. In this paper we evaluate experimentally the realistic effectiveness of several TMR schemes implemented with different levels of granularity. We measure and compare the dynamic cross-section of the TMRd circuits as well as number of accumulated bit-flips that cause a functional error. Additionally, we analyze and evaluate the effectiveness of both partial and full reconfiguration in both coarse and fine grained TMR schemes. As experimental results demonstrate, coarse-grained TMR efficiency and efficacy may be higher than a fine-grained TMR when partial reconfiguration is available.


FPGA TMR Fault tolerance Reliability Radiation effects 


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  1. 1.
    Dodd, P.E., Massengill, L.W.: Basic Mechanism and Modeling of Single-Event Upset in Digital Microelectronics. IEEE Transactions on Nuclear Science 50(3), 583–602 (2003)CrossRefGoogle Scholar
  2. 2.
    Quinn, H., Morgan, K., Graham, P., Krone, J., Caffrey, M.: Static proton and heavy ion testing of the xilinx virtex-5 device. In: 2007 IEEE Radiation Effects Data Workshop, pp. 177–184. IEEE, New York (2007)Google Scholar
  3. 3.
    Manuzzato, A., Gerardin, S., Paccagnella, A., Sterpone, L., Violante, M.: Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs. IEEE Transactions on Nuclear Science 55(4), 1968–1973 (2008)CrossRefGoogle Scholar
  4. 4.
    Niknahad, M., Sander, O., Becker, J.: Fine grain fault tolerance - a key to high reliability for FPGAs in space. In: 2012 IEEE Aerospace Conference, pp. 1–10. IEEE, New York (2012)Google Scholar
  5. 5.
    Kastensmidt, F.L., Sterpone, L., Carro, L., Reorda, M.S.: On the optimal design of triple modular redundancy logic for SRAM-based FPGAs. In: 2005 Design, Automation and Test in Europe, pp. 1290–1295. IEEE, New York (2005)Google Scholar
  6. 6.
    Wang, X.: Partitioning triple modular redundancy for single event upset mitigation in FPGA. In: 2010 International Conference on E-Product E-Service and E-Entertainment, pp. 1–4. IEEE, New York (2010)Google Scholar
  7. 7.
    Single-Event Upset Mitigation Selection Guide.
  8. 8.
    Berg, M., Poivey, C., Petrick, D., Espinosa, D., Lesea, A., LaBel, K.A., Friendlich, M., Kim, H., Phan, A.: Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis. IEEE Transactions on Nuclear Science 55(4), 2259–2266 (2008)CrossRefGoogle Scholar
  9. 9.
    Ostler, P.S., Caffrey, M.P., Gibelyou, D.S., Graham, P.S., Morgan, K.S., Pratt, B.H., Quinn, H.M., Wirthlin, M.J.: SRAM FPGA Reliability Analysis for Harsh Radiation Environments. IEEE Transactions on Nuclear Science 56(6), 3519–3526 (2009)CrossRefGoogle Scholar
  10. 10.
    Swartzlander, E.E., Young, W.W., Gibelyou, D.S., Joseph, S.J.: A Radix 4 Delay Commutator for Fast Fourier Transform Processor Implementation. IEEE Journal of Solid-state Circuits SC–19(5), 702–709 (1984)CrossRefGoogle Scholar
  11. 11.
    Virtex-5 Family Overview.
  12. 12.
    Violante, M., Sterpone, L., Manuzzato, A., Gerardin, S., Rech, P., Bagatin, M., Paccagnella, A., Andreani, C., Gorini, G., Pietropaolo, A., Cardarilli, G., Pontarelli, S., Frost, C.: A New Hardware/Software Platform and a New 1/E Neutron Source for Soft Error Studies: Testing FPGAs at the ISIS Facility. IEEE Transactions on Nuclear Science 54(4), 1184–1189 (2007)CrossRefGoogle Scholar
  13. 13.
    Tarrillo, J., Escobar, F.A., Kastensmidt, F.L., Valderrama, C.: Dynamic partial reconfiguration manager. In: 5th IEEE Latin American Symposium on Circuits and Systems, pp. 1–4. IEEE, New York (2014)Google Scholar
  14. 14.
    Device Reliability Report First Quarter 2014.

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Lucas A. Tambara
    • 1
    Email author
  • Felipe Almeida
    • 1
  • Paolo Rech
    • 1
  • Fernanda L. Kastensmidt
    • 1
  • Giovanni Bruni
    • 2
  • Christopher Frost
    • 3
  1. 1.Instituto de Informáatica, PGMICROUniversidade Federal do Rio Grande do SulPorto AlegreBrazil
  2. 2.Dipartimento di Ingegneria dell’InformazioneUniversitá di PadovaPadovaItaly
  3. 3.Rutherford Appleton LaboratoryISISDidcotUK

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