Chapter

FPGAs and Parallel Architectures for Aerospace Applications

pp 61-74

A Fault Injection System for Measuring Soft Processor Design Sensitivity on Virtex-5 FPGAs

  • Nathan A. HarwardAffiliated withDepartment of Electrical and Computer Engineering, NSF Center for High Performance Reconfigurable Computing (CHREC), Brigham Young University Email author 
  • , Michael R. GardinerAffiliated withDepartment of Electrical and Computer Engineering, NSF Center for High Performance Reconfigurable Computing (CHREC), Brigham Young University
  • , Luke W. HsiaoAffiliated withDepartment of Electrical and Computer Engineering, NSF Center for High Performance Reconfigurable Computing (CHREC), Brigham Young University
  • , Michael J. WirthlinAffiliated withDepartment of Electrical and Computer Engineering, NSF Center for High Performance Reconfigurable Computing (CHREC), Brigham Young University

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Abstract

This paper presents an FPGA fault injection system, a methodology for soft processor fault injection, and fault injection experimental results for MicroBlaze and LEON3 soft processor designs. The Xilinx Radiation Test Consortium—Virtex 5 Fault Injector (XRTC-V5FI) was built to evaluate the configuration memory sensitivity of soft processor designs. To overcome some of the challenges of soft processor fault injection, we designed the XRTC-V5FI to be fast, flexible, and to fully cover all configuration memory bits. The minimum time to inject a full bitstream is 28 minutes and the individual fault injection can be as fast as 49 μS. The LEON3 has 81.3 % more sensitive bits than the MicroBlaze, yet when normalized by the number of used slices, the MicroBlaze is 26.2 % more sensitive than the LEON3.