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Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures

  • Ali Azarian
  • João M. P. Cardoso
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8806)

Abstract

In recent years, there has been increasing interest on using task-level pipelining to accelerate the overall execution of applications mainly consisting of producer/consumer tasks. This paper presents coarse/fine-grained data flow synchronization approaches to achieve pipelining execution of the producer/consumer tasks in FPGA-based multicore architectures. Our approaches are able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the producer/consumer tasks. The experimental results show the feasibility of the approach when dealing with producer/consumer tasks with out-of-order communication and reveal noticeable performance improvements for a number of benchmarks over a single core implementation and not using task-level pipelining.

Keywords

Multicore Architectures Task-level Pipelining FPGA Producer/Consumer Data synchronization 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Ali Azarian
    • 1
  • João M. P. Cardoso
    • 1
  1. 1.Faculty of EngineeringUniversity of Porto and INESC-TECPortoPortugal

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