Advertisement

Library Support for Resource Constrained Accelerators

  • Laust Brock-Nannestad
  • Sven Karlsson
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8766)

Abstract

Accelerators, and other resource constrained systems, are increasingly being used in computer systems. Accelerators provide power efficient performance and often provide a shared memory model. However, it is a challenge to map feature rich APIs, such as OpenMP, to resource constrained systems. In this paper, we present a lightweight system where an accelerator can remotely execute library functions on a host processor. The implementation takes up 750 bytes but can replace arbitrary library calls leading to significant savings in memory foot print. We evaluate with a set of SPLASH-2 applications and show that the impact on execution time is negligible when compared to GCCs OpenMP implementation.

Keywords

Shared Memory Library Function Object Code Host Processor Cell Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    The ZeptoOS project, http://www.zeptoos.org, (accessed: July15, 2014)
  2. 2.
    Adapteva: Epiphany architecture reference, revision 14.03.11 (2014)Google Scholar
  3. 3.
    Jeun, W.C., Ha, S.: Effective openmp implementation and translation for multiprocessor system-on-chip without using os. In: Proceedings of the 2007 Asia and South Pacific Design Automation Conference, pp. 44–49. IEEE Computer Society (2007)Google Scholar
  4. 4.
    Lange, J., Pedretti, K., Hudson, T., Dinda, P., Cui, Z., Xia, L., Bridges, P., Gocke, A., Jaconette, S., Levenhagen, M., et al.: Palacios and kitten: New high performance operating systems for scalable virtualized and native supercomputing. In: 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), pp. 1–12. IEEE (2010)Google Scholar
  5. 5.
    Liu, F., Chaudhary, V.: A practical openmp compiler for system on chips. In: Voss, M.J. (ed.) WOMPAT 2003. LNCS, vol. 2716, pp. 54–68. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  6. 6.
    O’Brien, K., O’Brien, K., Sura, Z., Chen, T., Zhang, T.: Supporting openmp on cell. International Journal of Parallel Programming 36(3), 289–311 (2008)CrossRefzbMATHGoogle Scholar
  7. 7.
    OpenMP Architecture Review Board: Openmp application program interface, version 4.0 (2013)Google Scholar
  8. 8.
    Pakin, S., Lang, M., Kerbyson, D.: The reverse-acceleration model for programming petascale hybrid systems. IBM Journal of Research and Development 53(5), 1–8 (2009)CrossRefGoogle Scholar
  9. 9.
    Stotzer, E., Jayaraj, A., Ali, M., Friedmann, A., Mitra, G., Rendell, A.P., Lintault, I.: Openmp on the low-power ti keystone ii arm/dsp system-on-chip. In: Rendell, A.P., Chapman, B.M., Müller, M.S. (eds.) IWOMP 2013. LNCS, vol. 8122, pp. 114–127. Springer, Heidelberg (2013)CrossRefGoogle Scholar
  10. 10.
    University of Delaware, CAPSL: The modified splash-2 home page (2007), http://www.capsl.udel.edu/splash/, (accessed: July 15, 2014)
  11. 11.
    Wei, H., Yu, J.: Loading openmp to cell: An effective compiler framework for heterogeneous multi-core chip. In: Chapman, B., Zheng, W., Gao, G.R., Sato, M., Ayguadé, E., Wang, D. (eds.) IWOMP 2007. LNCS, vol. 4935, pp. 129–133. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  12. 12.
    Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The splash-2 programs: Characterization and methodological considerations. In: ACM SIGARCH Computer Architecture News, vol. 23, pp. 24–36. ACM (1995)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Laust Brock-Nannestad
    • 1
  • Sven Karlsson
    • 1
  1. 1.Technical University of DenmarkLyngbyDenmark

Personalised recommendations