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Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip

  • Zhen Zhang
  • Wendelin Serwe
  • Jian Wu
  • Tomohiro Yoneda
  • Hao Zheng
  • Chris Myers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8718)

Abstract

A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems if improperly implemented. Formal verification techniques are needed to check the correctness of the design. This paper performs formal analysis on an extension of the link-fault tolerant Network-on-Chip architecture introduced by Wu et al that supports multiflit wormhole routing. This paper describes several lessons learned during the process of constructing a formal model of this routing architecture. Finally, this paper presents how the deadlock freedom and tolerance to a single-link fault is verified for a two-by-two mesh version of this routing architecture.

Keywords

LNT process algebra fault-tolerant routing Network-on-Chip formal verification 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Zhen Zhang
    • 1
  • Wendelin Serwe
    • 2
  • Jian Wu
    • 3
  • Tomohiro Yoneda
    • 4
  • Hao Zheng
    • 5
  • Chris Myers
    • 1
  1. 1.Dept. of Elec. & Comp. Eng.Univ. of UtahSalt Lake CityUSA
  2. 2.INRIA & Univ. of Grenoble, LIGGrenobleFrance
  3. 3.Marvell Technology Group Ltd.Santa ClaraUSA
  4. 4.National Institute of InformaticsTokyoJapan
  5. 5.Dept. of Comp. Sci. and Eng.Univ. of S. FloridaTampaUSA

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