Execution and Verification of UML State Machines with Erlang

  • Ricardo J. Rodríguez
  • Lars-Åke Fredlund
  • Ángel Herranz
  • Julio Mariño
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8702)

Abstract

Validation of a system design enables to discover specification errors before it is implemented (or tested), thus hopefully reducing the development cost and time. The Unified Modelling Language (UML) is becoming widely accepted for the early specification and analysis of requirements for safety-critical systems, although a better balance between UML’s undisputed flexibility, and a precise unambiguous semantics, is needed. In this paper we introduce UMerL, a tool that is capable of executing and formally verifying UML diagrams (namely, UML state machine, class and object diagrams) by means of a translation of its behavioural information into Erlang. The use of the tool is illustrated with an example in embedded software design.

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Ricardo J. Rodríguez
    • 1
  • Lars-Åke Fredlund
    • 1
  • Ángel Herranz
    • 1
  • Julio Mariño
    • 1
  1. 1.Universidad Politécnica de MadridSpain

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