DReAM: Per-Task DRAM Energy Metering in Multicore Systems

  • Qixiao Liu
  • Miquel Moreto
  • Jaume Abella
  • Francisco J. Cazorla
  • Mateo Valero
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8632)


Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, such as per-task energy-aware task scheduling and energy-aware billing in datacenters. In particular, the contributions of this paper are (i) an ideal per-task energy metering model for DRAM memories; (ii) DReAM, an accurate, yet low cost, implementation of the ideal model (less than 5% accuracy error when 16 tasks share memory); and (iii) a comparison with standard methods (even distribution and access-count based) proving that DReAM is more accurate than these other methods.


Memory Access Multicore System Memory Controller Average Prediction Error Last Level Cache 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Barroso, L.: The Price of Performance. Queue 3(7) (2005)Google Scholar
  2. 2.
    Hamilton, J.: Internet-Scale Service Infrastructure Efficiency. In: ISCA (2009)Google Scholar
  3. 3.
    Jimenez, V., Gioiosa, R., Cazorla, F., Valero, M., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P.: Energy-aware accounting and billing in large-scale computing facilities. IEEE Micro 31(3), 60–71 (2011)CrossRefGoogle Scholar
  4. 4.
    Bircher, W.L., John, L.K.: Complete system power estimation: A trickle-down approach based on performance events. In: ISPASS (April 2007)Google Scholar
  5. 5.
    Liu, Q., Moreto, M., Jimenez, V., Abella, J., Cazorla, F.J., Valero, M.: Hardware support for accurate per-task energy metering in multicore systems. ACM Trans. Archit. Code Optim. 10(4) (December 2013)Google Scholar
  6. 6.
    Intel Corp.: Intel 64 and ia-32 architectures software developer’s manual (2012)Google Scholar
  7. 7.
    Phansalkar, A., Joshi, A., John, L.K.: Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. In: ISCA, pp. 412–423 (2007)Google Scholar
  8. 8.
    Pathak, A., Hu, C., Zhang, M., Bahl, P., Wang, W.M.: Fine-grained power modeling for smartphones using system call tracing. In: EuroSys. (2011)Google Scholar
  9. 9.
    Chung, Y.F., Lin, C.Y., King, C.T.: ANEPROF: Energy profiling for android java virtual machine and applications. In: ICPADS (2011)Google Scholar
  10. 10.
    David, H., Gorbatov, E., Hanebutte, U.R., Khanna, R., Le, C.: RAPL: Memory power estimation and capping. In: ISLPED (2010)Google Scholar
  11. 11.
    Intel Corp.: Intel xeon processor E5-2600 product family uncore performance monitoring guide (March 2012)Google Scholar
  12. 12.
    Shen, K., Shriraman, A., Dwarkadas, S., Zhang, X., Chen, Z.: Power containers: an os facility for fine-grained power and energy management on multicore servers. In: ASPLOS (2013)Google Scholar
  13. 13.
    Bellosa, F.: The benefits of event-driven energy accounting in power-sensitive systems. In: ACM SIGOPS European Workshop, pp. 37–42 (2000)Google Scholar
  14. 14.
    Kestor, G., Gioiosa, R., Kerbyson, D., Hoisie, A.: Quantifying the energy cost of data movement in scientific applications. In: IISWC, pp. 56–65 (September 2013)Google Scholar
  15. 15.
    Rosenfeld, P., Cooper-Balis, E., Jacob, B.: DRAMSim2: A cycle accurate memory system simulator. IEEE Comput. Archit. Lett. (2011)Google Scholar
  16. 16.
    Micron: Calculating memory system power for DDR3. Micron Technical Notes (2007)Google Scholar
  17. 17.
    Deng, Q., Meisner, D., Ramos, L., Wenisch, T., Bianchini, R.: Memscale: Active low-power modes for main memory. In: ASPLOS (2011)Google Scholar
  18. 18.
    Acosta, C., Cazorla, F., Ramirez, A., Valero, M.: The MPsim simulation tool. Technical Report UPC-DAC-RR-CAP-2009-15, UPC (2009)Google Scholar
  19. 19.
    Sherwood, T., Perelman, E., Calder, B.: Basic block distribution analysis to find periodic behavior and simulation points in applications. In: PACT (2001)Google Scholar
  20. 20.
    Brooks, D.M., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: ISCA (2000)Google Scholar
  21. 21.
    Muralimanohar, N., Balasubramonian, R., Jouppi, N.: CACTI 6.0: A tool to understand large caches. HP Tech Report HPL-2009-85 (2009)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Qixiao Liu
    • 1
    • 2
  • Miquel Moreto
    • 1
    • 2
  • Jaume Abella
    • 1
  • Francisco J. Cazorla
    • 1
    • 2
    • 3
  • Mateo Valero
    • 1
    • 2
  1. 1.Barcelona Supercomputing CenterBarcelonaSpain
  2. 2.Universitat Politecnica de CatalunyaBarcelonaSpain
  3. 3.Spanish National Research Council (IIIA-CSIC)BarcelonaSpain

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