Generating Core in Rough Set Theory: Design and Implementation on FPGA

  • Maciej Kopczynski
  • Tomasz Grzes
  • Jaroslaw Stepaniuk
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8537)


In this paper we propose the FPGA based device for data processing using rough set methods. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting core generation in comparison to software implementation.


Rough sets FPGA hardware core 


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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Maciej Kopczynski
    • 1
  • Tomasz Grzes
    • 1
  • Jaroslaw Stepaniuk
    • 1
  1. 1.Faculty of Computer ScienceBialystok University of TechnologyBialystokPoland

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