SystemC Modeling with Transaction Events

Chapter
First Online:
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 311)

Abstract

Today, in the design of embedded systems several abstraction levels are used ranging from register transfer level to transaction level. In this contribution we will introduce a new SystemC modeling technique with transaction events for communication modeling. Transaction events extend traditional timed events with a communication payload, thus combining state update and process triggering. This modeling technique can be used at all abstraction levels to create deterministic simulation models in a conceptual clean way.

Keywords

SystemC Transaction-Level Modeling (TLM) OSCI TLM-2.0 Register Transfer Level (RTL) Bus modeling Transaction Level (TL) modeling styles Deterministic simulation Preemption modeling Parallel simulation AMBA High-performance Bus (AHB) 
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References

  1. 1.
    OSCI TLM-2.0 Language Reference Manual (JA32). Open SystemC Initiative (OSCI) TLM Working GroupGoogle Scholar
  2. 2.
    Standard SystemC Language Reference Manual, IEEE Standard 1666–2011. IEEE Computer SocietyGoogle Scholar
  3. 3.
    (ARM) ARML (1999) AMBA specification (Revision 2.0), ARM IHI 0011A. http://www.arm.com
  4. 4.
    (ARM) ARML (2003) AMBA AHB cycle level interface (AHB CLI) specification. http://www.arm.com
  5. 5.
    Burton M, Aldis J, Guenzel R, Klingauf W (2007) Transaction level modeling: a reflection on what TLM is and how TLMs may be classified. In: Proceedings of the forum on specification and design languages (FDL) 2007Google Scholar
  6. 6.
    Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proceedings of the conference on hardware/software codesign and system synthesis (CODES+ISSS) 2007. doi: 10.1109/CODESS.2003.1275250
  7. 7.
    Caldari M, Conti M, Coppola M, Curaba S, Pieralisi L, Turchetti C (2003) Transaction-level models for AMBA bus architecture using SystemC 2.0. In: Proceedings of the conference on design, automation and test in Europe (DATE) 2003. doi: 10.1109/DATE.2003.1253800
  8. 8.
    Combes P, Caron E, Desprez F, Chopard B, Zory J (2008) Relaxing synchronization in a parallel SystemC kernel. In: Proceedings of the international symposium on parallel and distributed processing with applications (ISPA) 2008, pp 180–187. doi: 10.1109/ISPA.2008.124
  9. 9.
    Ezudheen P, Chandran P, Chandra J, Simon B, Ravi D (2009) Parallelizing systemC kernel for fast hardware simulation on SMP machines. In: Proceedings of the workshop on principles of advanced and distributed simulation (PADS) 2009, pp 80–87. doi: 10.1109/PADS.2009.25
  10. 10.
    Fujimoto R (2000) Parallel and distributed simulation systems. Wiley, New YorkGoogle Scholar
  11. 11.
    Groetker T, Liao S, Martin G, Swan S (2002) System design with SystemC. Kluwer Academic Publishers, DordrechtGoogle Scholar
  12. 12.
    Huang K, Bacivarov I, Hugelshofer F, Thiele L (2008) Scalably distributed SystemC simulation for embedded applications. In: International symposium on industrial embedded systems (SIES) 2008, pp 271–274. doi: 10.1109/SIES.2008.4577715
  13. 13.
    Indrusiak LS, dos Santos OM (2011) Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration. In: Proceedings of the conference on design, automation and test in Europe (DATE) 2011. doi: 10.1109/DATE.2011.5763179
  14. 14.
    Kohler A, Radetzki M (2009) A SystemC TLM2 model of communication in wormhole switched networks-on-chip. In: Proceedings of the forum on specification and design languages (FDL) 2009Google Scholar
  15. 15.
    Pasricha S, Dutt N (2010) On-chip communication architectures: system on chip interconnect. Systems on silicon. Elsevier Science, AmsterdamGoogle Scholar
  16. 16.
    Pasricha S, Dutt N, Ben-Romdhane M (2004) Extending the transaction level modeling approach for fast communication architecture exploration. In: Proceedings of the design automation conference (DAC) 2004Google Scholar
  17. 17.
    Pasricha S, Dutt N, Ben-Romdhane M (2008) Fast exploration of bus-based communication architectures at the CCATB abstraction. ACM Trans Embedded Comput Syst 7(2):217–226. doi: 10.1145/1331331.1331346
  18. 18.
    Radetzki M, Salimi Khaligh R (2007) Modelling alternatives for cycle approximate bus TLMs. In: Proceedings of the forum on specification and design languages (FDL) 2007Google Scholar
  19. 19.
    Radetzki M, Salimi Khaligh R (2008) Accuracy-adaptive simulation of transaction level models. In: Proceedings of the conference on design, automation and test in Europe (DATE) 2008. doi: 10.1109/DATE.2008.4484912
  20. 20.
    Rose A, Swan S, Pierce J, Fernandez JM et al (2005) Transaction level modeling in SystemC. http://www.systemc.org
  21. 21.
    Roth C, Reder S, Sander O, Hübner M, Becker J (2012) A framework for exploration of parallel SystemC simulation on the single-chip cloud computer. In: Proceedings of the conference on simulation tools and techniques (SIMUTOOLS) 2012, pp 202–207Google Scholar
  22. 22.
    Schirner G, Doemer R (2005) System level modeling of an AMBA bus. Technical report, Center for Embedded Computer Systems, University of CaliforniaGoogle Scholar
  23. 23.
    Schirner G, Doemer R (2009) Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ACM Trans Embedded Comput Syst (TECS) 8(1). doi: 10.1145/1457246.1457250
  24. 24.
    Schumacher C, Leupers R, Petras D, Hoffmann A (2010) parSC: synchronous parallel SystemC simulation on multi-core host architectures. In: Proceedings of the conference on hardware/software codesign and system synthesis (CODES+ISSS) 2010, pp 241–246Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Embedded Systems Engineering GroupUniversity of StuttgartStuttgartGermany

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