Assisting Refinement in System-on-Chip Design

  • Hocine Mokrani
  • Rabéa Ameur-Boulifa
  • Emmanuelle Encrenaz-Tiphene
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 311)

Abstract

With the increasing complexity of systems on chip, designers have adopted layered design methodologies, where the description of systems is made by steps. Currently, those methods do not ensure the preservation of properties in the process of system development. In this paper, we present a system on chip design method, based on model transformations—or refinements—in order to guarantee the preservation of functional correctness along the design flow. We also provide experimental results showing the benefits of the approach when property verification is concerned.

Keywords

System on a Chip (SoC) Architecture exploration Platform-Based Design (PBD) System modeling Formal verification Communication refinement Property-preservation checking 

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Hocine Mokrani
    • 1
  • Rabéa Ameur-Boulifa
    • 1
  • Emmanuelle Encrenaz-Tiphene
    • 2
    • 3
  1. 1.Institut Télécom, Télécom ParisTech, CNRS-LTCISophia-AntipolisFrance
  2. 2.Sorbonne Universités, Université Pierre et Marie Curie Paris 6UMR 7606, LIP6ParisFrance
  3. 3.CNRSUMR 7606, LIP6ParisFrance

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