On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure
It is common for large hardware designs to have a number of registers or memories of which the contents have to be changed very seldom, e.g. only at startup. The conventional way of accessing these memories is using a low-speed memory bus. This bus uses valuable hardware resources, introduces long, global connections and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used.
A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.
KeywordsFPGA HPC partial reconfiguration block RAM
Unable to display preview. Download preview PDF.
- 1.Pell, O., Mencer, O., Tsoi, K.H., Luk, W.: Maximum Performance Computing with Dataflow Engines. In: High-Performance Computing Using FPGAs, pp. 747–774 (2013)Google Scholar
- 2.Beckhoff, C., Koch, D., Torresen, J.: GoAhead: A Partial Reconfiguration Framework. In: IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 37–44 (2012)Google Scholar
- 3.Xilinx: Partial Reconfiguration User Guide (2010)Google Scholar
- 4.Bruneel, K., Heirman, W., Stroobandt, D.: Dynamic Data Folding with Parameterizable FPGA Configurations. ACM Transactions on Design Automation of Electronic Systems (TODAES) 16(4), 43:1–43:29 (2011)Google Scholar
- 5.Shelburne, M., Patterson, C., Athanas, P., Jones, M., Martin, B., Fong, R.: MetaWire: Using FPGA Configuration Circuitry to Emulate a Network-on-Chip. In: International Conf. on Field Programmable Logic and Applications, pp. 257–262 (2008)Google Scholar
- 6.Xilinx: Virtex-6 FPGA Configuration User Guide (2012)Google Scholar
- 7.Xilinx: Virtex-5 FPGA Configuration User Guide (2012)Google Scholar
- 8.Xilinx: XAPP290 Difference-Based Partial Reconfiguration, 1–11 (2007)Google Scholar
- 9.Cattaneo, R., Pilato, C., Mastinu, M., Kadlcek, O., Pell, O., Santambrogio, M.: Runtime Adaptation on Dataflow HPC Platforms. In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 84–91 (2013)Google Scholar