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Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer

  • Tobias Kenter
  • Gavin Vaz
  • Christian Plessl
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8405)

Abstract

In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector coprocessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.

Keywords

Heterogeneous System Binary Acceleration Outer-Loop Vectorization 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Tobias Kenter
    • 1
  • Gavin Vaz
    • 1
  • Christian Plessl
    • 1
  1. 1.Department of Computer ScienceUniversity of PaderbornGermany

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