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Exploring Irregular Reduction Support in Transactional Memory

  • Miguel A. Gonzalez-Mesa
  • Ricardo Quislant
  • Eladio Gutierrez
  • Oscar Plata
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8285)

Abstract

Transactional memory (TM) has emerged as an alternative to the lock-based parallel programming model offering an effective and optimistic management of concurrency. Recently, TM is being experimented in the context of high performance computing. Many applications in that area spent a large amount of computing time in irregular reduction operations, so their efficient parallelization is of utmost importance. This paper explores how to address irregular reductions in the TM model, analyzing which support needs to be added to the TM system to deal with reductions as a special case of conflicting memory accesses.

Keywords

Tional Memory Atomic Operation Memory Overhead Reduction Object Transaction Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Ansari, M., Kotselidis, C., Jarvis, K., Luján, M., Kirkham, C., Watson, I.: Advanced concurrency control for transactional memory using transaction commit rate. In: Luque, E., Margalef, T., Benítez, D. (eds.) Euro-Par 2008. LNCS, vol. 5168, pp. 719–728. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  2. 2.
    Bihari, B.L.: Transactional memory for unstructured mesh simulations. J. Scientific Computing 54(2-3), 311–332 (2013)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Feautrier, P.: Array expansion. In: 2nd Int’l Conf. on Supercomputing (ICS 1988), pp. 429–441 (1988)Google Scholar
  4. 4.
    Felber, P., Fetzer, C., Marlier, P., Riegel, T.: Time-based software transactional memory. IEEE Trans. on Parallel and Distributed Systems 21(12), 1793–1807 (2010)CrossRefGoogle Scholar
  5. 5.
    Gutiérrez, E., Plata, O., Zapata, E.: A compiler method for the parallel execution of irregular reductions in scalable shared memory multiprocessors. In: 14th Int. Conf. on Supercomputing (ICS 2000), pp. 78–87 (2000)Google Scholar
  6. 6.
    Hall, M., Anderson, J., Amarasinghe, S., Murphy, B., Liao, S., Bu, E.: Maximizing multiprocessor performance with the suif compiler. IEEE Computer 29(12), 84–89 (1996)CrossRefGoogle Scholar
  7. 7.
    Han, H., Tseng, C.: Exploiting locality for irregular scientific codes. IEEE Trans. on Parallel and Distributed Systems 17(7), 606–618 (2006)CrossRefGoogle Scholar
  8. 8.
    Harris, T., Larus, J.R., Rajwar, R.: Transactional Memory, 2nd edn. Morgan & Claypool Publishers, USA (2010)Google Scholar
  9. 9.
    Intel: Intel 64 and IA-32 Architectures Software Developer’s Manual – Volume 3: System Programming Guide. Intel Corporation, Santa Clara, CA, USA (2013)Google Scholar
  10. 10.
    Jain, T., Agrawal, T.: The Haswell microarchitecture – 4th generation processor. International Journal of Computer Science and Information Technologies 4(3), 477–480 (2013)Google Scholar
  11. 11.
    Johnson, N.P., Kim, H., Prabhu, P., Zaks, A., August, D.I.: Speculative separation for privatization and reductions. In: 33rd ACM SIGPLAN Conf. on Programming Language Design and Implementation (PLDI 2012), pp. 359–370 (2012)Google Scholar
  12. 12.
    Larus, J., Kozyrakis, C.: Transactional memory. Communications of the ACM 51(7), 80–88 (2008)CrossRefGoogle Scholar
  13. 13.
    McDonald, A., Chung, J., Carlstrom, B.D., Minh, C.C., Chafi, H., Kozyrakis, C., Olukotun, K.: Architectural semantics for practical transactional memory. In: 33rd Int’l. Symp. on Computer Architecture (ISCA 2006), pp. 53–65 (2006)Google Scholar
  14. 14.
    Yu, H., Rauchwerger, L.: An adaptive algorithm selection framework for reduction parallelization. IEEE Trans. on Parallel and Distributed Systems 17(10), 1084–1096 (2006)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2013

Authors and Affiliations

  • Miguel A. Gonzalez-Mesa
    • 1
  • Ricardo Quislant
    • 1
  • Eladio Gutierrez
    • 1
  • Oscar Plata
    • 1
  1. 1.Dept. Computer ArchitectureUniversity of MalagaMalagaSpain

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