Exploring Irregular Reduction Support in Transactional Memory

  • Miguel A. Gonzalez-Mesa
  • Ricardo Quislant
  • Eladio Gutierrez
  • Oscar Plata
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8285)


Transactional memory (TM) has emerged as an alternative to the lock-based parallel programming model offering an effective and optimistic management of concurrency. Recently, TM is being experimented in the context of high performance computing. Many applications in that area spent a large amount of computing time in irregular reduction operations, so their efficient parallelization is of utmost importance. This paper explores how to address irregular reductions in the TM model, analyzing which support needs to be added to the TM system to deal with reductions as a special case of conflicting memory accesses.


Tional Memory Atomic Operation Memory Overhead Reduction Object Transaction Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer International Publishing Switzerland 2013

Authors and Affiliations

  • Miguel A. Gonzalez-Mesa
    • 1
  • Ricardo Quislant
    • 1
  • Eladio Gutierrez
    • 1
  • Oscar Plata
    • 1
  1. 1.Dept. Computer ArchitectureUniversity of MalagaMalagaSpain

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