A Hoare Logic for SIMT Programs

  • Kensuke Kojima
  • Atsushi Igarashi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8301)

Abstract

We study a Hoare Logic to reason about GPU kernels, which are parallel programs executed on GPUs. We consider the SIMT (Single Instruction Multiple Threads) execution model, in which multiple threads execute in lockstep (that is, execute the same instruction at a time). When control branches both branches are executed sequentially but during the execution of each branch only those threads that take it are enabled; after the control converges, all threads are enabled and execute in lockstep again. In this paper we adapt Hoare Logic to the SIMT setting, by adding an extra component representing the set of enabled threads to the usual Hoare triples. It turns out that soundness and relative completeness do not hold for all programs; a difficulty arises from the fact that one thread can invalidate the loop termination condition of another thread through shared memory. We overcome this difficulty by identifying an appropriate class of programs for which soundness and relative completeness hold.

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References

  1. 1.
    Owens, J.D., Luebke, D., Govindaraju, N., Harris, M., Krüger, J., Lefohn, A., Purcell, T.J.: A survey of general-purpose computation on graphics hardware. Computer Graphics Forum 26(1), 80–113 (2007)CrossRefGoogle Scholar
  2. 2.
    NVIDIA: NVIDIA CUDA C Programming Guide (2012)Google Scholar
  3. 3.
    Betts, A., Chong, N., Donaldson, A., Qadeer, S., Thomson, P.: GPUVerify: a verifier for GPU kernels. In: Proc. of the ACM International Conference on Object Oriented Programming Systems Languages and Applications. OOPSLA 2012, pp. 113–132. ACM, New York (2012)CrossRefGoogle Scholar
  4. 4.
    Collingbourne, P., Donaldson, A.F., Ketema, J., Qadeer, S.: Interleaving and lock-step semantics for analysis and verification of GPU kernels. In: Felleisen, M., Gardner, P. (eds.) Programming Languages and Systems. LNCS, vol. 7792, pp. 270–289. Springer, Heidelberg (2013)CrossRefGoogle Scholar
  5. 5.
    Collingbourne, P., Cadar, C., Kelly, P.H.: Symbolic crosschecking of floating-point and SIMD code. In: Proc. of the sixth conference on Computer systems, EuroSys 2011, pp. 315–328. ACM, New York (2011)Google Scholar
  6. 6.
    Collingbourne, P., Cadar, C., Kelly, P.H.J.: Symbolic testing of openCL code. In: Eder, K., Lourenço, J., Shehory, O. (eds.) HVC 2011. LNCS, vol. 7261, pp. 203–218. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  7. 7.
    Li, G., Gopalakrishnan, G.: Scalable SMT-based verification of GPU kernel functions. In: Proc. of the 18th ACM SIGSOFT International Symposium on Foundations of Software Engineering (FSE 2010), pp. 187–196. ACM (2010)Google Scholar
  8. 8.
    Li, G., Gopalakrishnan, G.: Parameterized verification of GPU kernel programs. In: 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), pp. 2450–2459 (May 2012)Google Scholar
  9. 9.
    Li, G., Li, P., Sawaya, G., Gopalakrishnan, G., Ghosh, I., Rajan, S.P.: GKLEE: concolic verification and test generation for GPUs. In: Proc. of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. PPoPP 2012, pp. 215–224. ACM, New York (2012)CrossRefGoogle Scholar
  10. 10.
    Li, P., Li, G., Gopalakrishnan, G.: Parametric flows: automated behavior equivalencing for symbolic analysis of races in CUDA programs. In: Proc. of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC 2012), pp. 29:1–29:10. IEEE Computer Society Press (2012)Google Scholar
  11. 11.
    Chiang, W.-F., Gopalakrishnan, G., Li, G., Rakamarić, Z.: Formal analysis of GPU programs with atomics via conflict-directed delay-bounding. In: Brat, G., Rungta, N., Venet, A. (eds.) NFM 2013. LNCS, vol. 7871, pp. 213–228. Springer, Heidelberg (2013)CrossRefGoogle Scholar
  12. 12.
    Huisman, M., Mihelčić, M.: Specification and verification of GPGPU programs using permission-based separation logic. In: Bytecode 2013, 8th Workshop on Bytecode Semantics, Verification, Analysis and Transformation (2013), http://hgpu.org/?p=9099
  13. 13.
    Apt, K.R., de Boer, F., Olderog, E.R.: Verification of Sequential and Concurrent Programs, 3rd edn. Springer Publishing Company, Incorporated (2009)Google Scholar
  14. 14.
    Habermaier, A., Knapp, A.: On the correctness of the SIMT execution model of GPUs. In: Seidl, H. (ed.) Programming Languages and Systems. LNCS, vol. 7211, pp. 316–335. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  15. 15.
    NVIDIA: Parallel Thread Execution ISA Version 3.1 (2012)Google Scholar
  16. 16.
    Tripakis, S., Stergiou, C., Lublinerman, R.: Checking equivalence of spmd programs using non-interference. Technical Report UCB/EECS-2010-11, EECS Department, University of California, Berkeley (January 2010)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2013

Authors and Affiliations

  • Kensuke Kojima
    • 1
    • 2
  • Atsushi Igarashi
    • 1
    • 2
  1. 1.Kyoto UniversityJapan
  2. 2.JST CRESTJapan

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