Arithmetic Bit-Level Verification Using Network Flow Model

  • Maciej Ciesielski
  • Walter Brown
  • André Rossi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8244)

Abstract

The paper presents a new approach to functional, bit-level verification of arithmetic circuits. The circuit is modeled as a network of adders and basic Boolean gates, and the computation performed by the circuit is viewed as a flow of binary data through such a network. The verification problem is cast as a Network Flow problem and solved using symbolic term rewriting and simple algebraic techniques. Functional correctness is proved by showing that the symbolic flow computed at the primary inputs is equal to the flow computed at the primary outputs. Experimental results show a potential application of the method to certain classes of arithmetic circuits.

Keywords

Formal verification Functional verification Arithmetic verification Bit-level arithmetic 

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Copyright information

© Springer International Publishing Switzerland 2013

Authors and Affiliations

  • Maciej Ciesielski
    • 1
  • Walter Brown
    • 1
  • André Rossi
    • 2
  1. 1.ECE DepartmentUniversity of MassachusettsAmherstUSA
  2. 2.Lab-STICC UMR 6285Université de Bretagne-SudLorient CedexFrance

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