Pre-bond TSV Test Through TSV Probing

  • Brandon Noia
  • Krishnendu Chakrabarty
Chapter
First Online:

Abstract

Chapter 3 discussed the need for pre-bond TSV test and explored cutting-edge research in TSV testing using BIST. Pre-bond testing allows for the detection of defects that are inherent in the manufacture of the TSV itself, such as impurities or voids, while post-bond testing detects faults caused by thinning, alignment, and bonding. Successful pre-bond defect screening can allow defective dies to be discarded before stacking. Moreover, pre-bond testing and diagnosis can facilitate defect localization and repair prior to bonding. Because methods to “unbond” die are yet to be realized, even one faulty die will compel us to discard the stacked IC, including all good dies in the stack. Pre-bond test is further required if wafer matching, die binning, or other methods for increasing stack yield are to be used, because they require KGD test to be completed for all dies on a wafer.

Keywords

Contact Resistance Test Group Test Time Leakage Test Charge Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in to check access.

References

  1. 26.
    P.-Y. Chen, W. C.-W. Wu, and D.-M. Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC Before Bonding”, Proc. IEEE VLSI Test Symposium, pp. 263–268, 2010.Google Scholar
  2. 27.
    D. Lewis and H.-H. Lee, “A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors”, Proc. International Test Conference, pp. 1–8, 2007.Google Scholar
  3. 35.
    E.J. Marinissen, J. Verbree, and M. Konijnenburg, “A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs”, VLSI Test Symposium, 2010.Google Scholar
  4. 37.
    B. Noia, K. Chakrabarty and E. J. Marinissen, “Optimization Methods for Post-bond Die-Internal/External Testing in 3D Stacked ICs”, Proc. IEEE International Test Conference, 2010.Google Scholar
  5. 38.
    H. Chen, J.-Y. Shih, S.-W. Li, H.-C. Lin, M.-J. Wang, C.-N. Peng. “Electrical Tests for Three-Dimensional ICs (3DICs) with TSVs.”, International Test Conference 3D-Test Workshop, 2010.Google Scholar
  6. 39.
    L. Jiang, Q. Xu, K. Chakrabarty, and T.M. Mak, “Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint”, International Conference on Computer-Aided Design, pp. 191–196, 2009.Google Scholar
  7. 40.
    U. Kang et. al., “8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology”, IEEE Solid-State Circuits, vol. 45, no. 1, pp. 111–119, 2010.Google Scholar
  8. 42.
    E.J. Marinissen and Y. Zorian, “Testing 3D Chips Containing Through-Silicon Vias”, International Test Conference, E 1.1, 2009.Google Scholar
  9. 43.
    H.-H.S. Lee and K. Chakrabarty, “Test Challenges for 3D Integrated Circuits”, IEEE Design & Test of Computers, vol. 26, pp. 26–35, September/October 2009.Google Scholar
  10. 45.
    K. Puttaswamy and G. H. Loh, “Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors,” IEEE High Performance Computer Architecture, pp. 193–204, 2007.Google Scholar
  11. 48.
    X. Wu, Y. Chen K. Chakrabarty, and Y. Xie, “Test-Access Mechanism Optimization for Core-Based Three-dimensional SOCs”, IEEE International Conference on Computer Design, pp. 212–218, 2008.Google Scholar
  12. 49.
    L. Jiang, L. Huang, and Q. Xu, “Test Architecture Design and Optimization for Three-Dimensional SoCs”, Design, Automation, and Test in Europe, pp. 220–225, 2009.Google Scholar
  13. 50.
    K. Lee, “Trends in Test”, Keynote talk presented at IEEE Asian Test Symposium, December 2010.Google Scholar
  14. 51.
    P. Holmberg, “Automatic Balancing of Linear AC Bridge Circuits for Capacitive Sensor Elements”, Instrumentation and Measurement Technology Conference, pp. 475–478, 2010.Google Scholar
  15. 52.
  16. 53.
    T. Yasafuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, “Effect of Resistance of TSV’s on Performance of Boost Converter for Low-Power 3D SSD with NAND Flash Memories”, 3D System Integration, pp. 1–4, 2009.Google Scholar
  17. 54.
    J. Broz and R. Rincon, “Probe Needle Wear and Contact Resistance”, talk presented at Southwestern Test Workshop, June 1998.Google Scholar
  18. 55.
    K. Kataoka, S. Kawamura, T. Itoh, T. Suga, K. Ishikawa, and H. Honma, “Low Contact-Force and Compliant MEMS Probe Card Utilizing Fritting Contact”, IEEE Conference on Micro Electro Mechanical Systems, pp. 364–367, 2002.Google Scholar
  19. 56.
    45nm PTM LP Model. http://ptm.asu.edu/modelcard/LP/45nm_LP.pm Accessed January 2011.
  20. 57.
    J. Leung, M. Zargari, B.A. Wooley, and S.S. Wong, “Active Substrate Membrane Probe Card”, Electron Devices Meeting, pp. 709–712, 1995.Google Scholar
  21. 58.
    D. Williams and T. Miers, “A Coplanar Probe to Microstrip Transition”, IEEE Transactions on Microwave Theory and Techniques, pp. 1219–1223, 1988.Google Scholar
  22. 59.
    O. Weeden, “Probe Card Tutorial”, http://www.accuprobe.com/Downloads/Probe%20Card%20Tutorial.pdf Accessed January 2010.
  23. 76.
    K. Smith et al., “Evaluation of TSV and Micro-Bump Probing for Wide I/O Testing”, Proc. IEEE International Test Conference, pp. 1–10, 2011.Google Scholar
  24. 77.
    O. Yaglioglu, and N. Eldridge, “Direct Connection and Testing of TSV and Microbump Devices Using NanoPierceTM Contactor for 3D-IC Integration” Proc. IEEE VLSI Test Symposium, pp. 96–101, 2012.Google Scholar
  25. 78.
    B. Leslie and F. Matta, “Wafer-Level Testing with a Membrane Probe”, IEEE Design and Test of Computers, pp. 10–17, 1989.Google Scholar
  26. 80.
    Y.-W. Yi, Y. Kondoh, K. Ihara, and M. Saitoh, “A Micro Active Probe Device Compatible with SOI-CMOS Technologies”, Microelectromechanical Systems, vol. 6, pp. 242–248, 1997.Google Scholar
  27. 81.
    W. Zhang, P. Limaye, R. Agarwal, and P. Soussan, “Surface Planarization of Cu/Sn Micro-bump and its Application in Fine Pitch Cu/Sn Solid State Diffusion Bonding”, Proc. Conf. on Electronics Packaging Technology, pp. 143–146, 2010.Google Scholar
  28. 82.
    Y. Ohara et al., “10 μm Fine Pitch Cu/Sn Micro-Bumps for 3-D Super-Chip Stack,” Proc. 3D System Integration, pp. 1–6, 2009.Google Scholar
  29. 83.
    G. Katti et al., “Temperature Dependent Electrical Characteristics of Through-Si-Via (TSV) Interconnections,” International Interconnect Technology Conference, pp. 1–3, 2010.Google Scholar
  30. 84.
    D. Velenis, E. J. Marinissen, and E. Beyne, “Cost Effectiveness of 3D Integration Options,” Proc. 3D Systems Integration Conference, pp. 1–6, 2010.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Brandon Noia
    • 1
  • Krishnendu Chakrabarty
    • 1
  1. 1.ECEDuke UniversityDurhamUSA

Personalised recommendations