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PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy

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Euro-Par 2021: Parallel Processing (Euro-Par 2021)

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Abstract

The ever-increasing gap between the processor and main memory speeds requires careful utilization of the limited memory link. This is additionally emphasized for the case of memory-bound applications. Prioritization of memory requests in the memory controller is one of the approaches to improve performance of such codes. However, current designs do not consider high-level information about parallel applications. In this paper, we propose a holistic approach to this problem, where the runtime system-level knowledge is made available in hardware. Processor exploits this information to better prioritize memory requests, while introducing negligible hardware cost. Our design is based on the notion of critical path in the execution of a parallel code. The critical tasks are accelerated by prioritizing their memory requests within the on-chip memory hierarchy. As a result, we reduce the critical path and improve the overall performance up to 1.19\(\times \) compared to the baseline systems.

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Notes

  1. 1.

    Section 4 describes the experimental setup in detail.

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Acknowledgements

This work has been partially supported by the Spanish Ministry of Science and Innovation (PID2019-107255GB-C21/AEI/10.13039/ 501100011033), by the Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328), by the European Union’s Horizon 2020 research and innovation program under the Mont-Blanc 2020 project (grant agreement 779877) and by the RoMoL ERC Advanced Grant (GA 321253). V. Dimić has been partially supported by the Agency for Management of University and Research Grants (AGAUR) of the Government of Catalonia under Ajuts per a la contractació de personal investigador novell fellowship number 2017 FI_B 00855. M. Moretó and M. Casas have been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowship numbers RYC-2016-21104 and RYC-2017-23269, respectively.

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Authors and Affiliations

  1. Barcelona Supercomputing Center (BSC), Barcelona, Spain

    Vladimir Dimić, Miquel Moretó, Marc Casas & Mateo Valero

  2. Universitat Politècnica de Catalunya (UPC), Barcelona, Spain

    Vladimir Dimić, Miquel Moretó, Marc Casas & Mateo Valero

Authors
  1. Vladimir Dimić
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  2. Miquel Moretó
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  3. Marc Casas
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  4. Mateo Valero
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Correspondence to Vladimir Dimić .

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Editors and Affiliations

  1. Universidade de Lisboa, Lisbon, Portugal

    Leonel Sousa

  2. Universidade de Lisboa, Lisbon, Portugal

    Nuno Roma

  3. Universidade de Lisboa, Lisbon, Portugal

    Pedro Tomás

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Dimić, V., Moretó, M., Casas, M., Valero, M. (2021). PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. In: Sousa, L., Roma, N., Tomás, P. (eds) Euro-Par 2021: Parallel Processing. Euro-Par 2021. Lecture Notes in Computer Science(), vol 12820. Springer, Cham. https://doi.org/10.1007/978-3-030-85665-6_37

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  • DOI: https://doi.org/10.1007/978-3-030-85665-6_37

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