Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm

  • Rui P. Duarte
  • Helena CruzEmail author
  • Horácio Neto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12083)


Synthetic Aperture Radar is a form of radar widely used to extract information about the surface of the target. The transformation of the signals into an image is based on DSP algorithms that perform intensive but repetitive computation over the signal data. Traditionally, an aircraft or satellite acquires the radar data streams and sends it to be processed on a data center to produce images faster. However, there are novel applications demanding on-board signal processing to generate images. This paper presents a novel implementation for an on-board embedded SoC of an accelerator for the Backprojection algorithm, which is the reference algorithm for producing images of SAR sensors. The methodology used is based on a HW/SW design partition, where the most time consuming computations are implemented in hardware. The accelerator was specified in HLS, which allows to reuse the code from the original implementation of the algorithm in software. The accelerator performs the computations using floating-point arithmetic to produce the same output as the original algorithm. The target SoC device is a Zynq 7020 from Xilinx which has a dual-core ARM-A9 processor along with a reconfigurable fabric which is used to implement the hardware accelerator. The proposed systems outperformed the software-only implementation in 7.7\(\times \) while preserving the quality of the image by adopting the same floating-point representations from the original software implementation.


FPGA Synthetic Aperture Radar DSP Backprojection Zynq SoC Reconfigurable accelerator 


  1. 1.
    Barker, K., et al.: PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. Pacific Northwest National Laboratory and Georgia Tech Research Institute, December 2013.
  2. 2.
    Cruz, H., Duarte, R.P., Neto, H.: Fault-tolerant architecture for on-board dual-core synthetic-aperture radar imaging. In: Hochberger, C., Nelson, B., Koch, A., Woods, R., Diniz, P. (eds.) ARC 2019. LNCS, vol. 11444, pp. 3–16. Springer, Cham (2019). Scholar
  3. 3.
    Gocho, M., Oishi, N., Ozaki, A.: Distributed parallel backprojection for real-time stripmap SAR imaging on GPU clusters. In: Proceedings - IEEE International Conference on Cluster Computing, ICCC 2017, September, pp. 619–620 (2017).
  4. 4.
    Lentaris, G., et al.: High-performance embedded computing in space: evaluation of platforms for vision-based navigation. J. Aerosp. Inf. Syst. 15(4), 178–192 (2018). Scholar
  5. 5.
    Pritsker, D.: Efficient global back-projection on an FPGA. In: 2015 IEEE Radar Conference (RadarCon), pp. 0204–0209, May 2015.
  6. 6.
    Song, X., Yu, W.: Processing video-SAR data with the fast backprojection method. IEEE Trans. Aerosp. Electron. Syst. 52(6), 2838–2848 (2016). Scholar
  7. 7.
    Wielage, M., Cholewa, F., Riggers, C., Pirsch, P., Blume, H.: Parallelization strategies for fast factorized backprojection SAR on embedded multi-core architectures. In: 2017 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), pp. 1–6. IEEE, November 2017.

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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.INESC-ID/IST-ULLisboaPortugal

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