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HLS-Based Acceleration Framework for Deep Convolutional Neural Networks

  • Ashish Misra
  • Volodymyr KindratenkoEmail author
Conference paper
  • 48 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12083)

Abstract

Deep Neural Networks (DNNs) have been successfully applied in many fields. Considering performance, flexibility, and energy efficiency, Field Programmable Gate Array (FPGA) based accelerator for DNNs is a promising solution. The existing frameworks however lack the possibility of reusability and friendliness to design a new network with minimum efforts. Modern high-level synthesis (HLS) tools greatly reduce the turnaround time of designing and implementing complex FPGA-based accelerators. This paper presents a framework for hardware accelerator for DNNs using high level specification. A novel architecture is introduced that maximizes data reuse and external memory bandwidth. This framework allows to generate a scalable HLS code for a given pre-trained model that can be mapped to different FPGA platforms. Various HLS compiler optimizations have been applied to the code to produce efficient implementation and high resource utilization. The framework achieves a peak performance of 23 frames per second for SqueezeNet on Xilinx Alveo u250 board.

Keywords

Accelerator design High level synthesis FPGA 

Notes

Acknowledgments

This work is funded by the National Science Foundation’s Major Research Instrumentation program, grant #1725729. We thank Yuan Ma for his help in setting up the simulation using Caffe and Tanitpong Lawphongpanich for his contribution with TensorFlow testing.

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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.University of IllinoisUrbanaUSA

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