Technique for Vendor and Device Agnostic Hardware Area-Time Estimation

  • Deshya WijesunderaEmail author
  • Kushagra Shah
  • Kisaru Liyanage
  • Alok Prakash
  • Thambipillai Srikanthan
  • Thilina Perera
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12083)


This work proposes a novel technique for hardware area-time estimation of applications on FPGA. The application C code is first converted to the target independent LLVM IR prior to wrapping the basic blocks as functions using a LLVM transformation pass. The LegUp tool’s ‘LLVM IR functions to RTL modules’ conversion is carried out to facilitate RTL synthesis using the Altera Quartus tools. In order to support FPGAs other than Altera, the soft IP cores generated by LegUp were replaced as generic RTL components. Further, additional modules have been incorporated to support floating point operations. This approach, has made it possible to support FPGAs from other vendors with high area-time estimation accuracy. The proposed technique relies on the free versions of the vendor tools and LegUp. Moreover, the approach does not necessitate time consuming post synthesis steps such as Place & Route and Bit Stream Generation in order to obtain reasonably accurate area estimation measures.


Generic Hardware estimation FPGA 


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Deshya Wijesundera
    • 1
    Email author
  • Kushagra Shah
    • 1
  • Kisaru Liyanage
    • 1
  • Alok Prakash
    • 1
  • Thambipillai Srikanthan
    • 1
  • Thilina Perera
    • 1
  1. 1.Nanyang Technological UniversitySingaporeSingapore

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