Advertisement

An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator

  • Mate CobrnicEmail author
  • Alen Duspara
  • Leon Dragic
  • Igor Piljic
  • Hrvoje Mlinaric
  • Mario Kovac
Conference paper
  • 141 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12043)

Abstract

In this paper is presented an area efficient reusable architecture for integer one dimensional Discrete Cosine Transform (1D DCT) with adjustable transform sizes in High Efficiency Video Coding (HEVC). Optimization is based on exploiting of symmetry and subset properties of the transform matrix. The proposed multiply-accumulate architecture is fully pipelined and applicable for all transform sizes. It provides the interface over which the processing system can control the datapath of the transform process and the synchronization channel that enables the system to receive the feedback information about utilization from the device. An intuitive line approach for calculating transform coefficients for all transform sizes was used instead of the commonly applied recursive decomposition approach. This approach simplifies disabling of lines that are not employed for a particular transform size. The proposed architecture is implemented on the FPGA platform, can operate at 407,5 MHz, achieves throughput of 815 Msps and can support encoding of a 4K UHD@30 fps video sequence in real time.

Keywords

Integer Discrete Cosine Transform (DCT) High Efficiency Video Coding (HEVC) Field-Programmable Gate Array (FPGA) Pipelined architecture 

Notes

Acknowledgements

The work presented in this paper has been partially funded by the European Processor Initiative project that has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 826647.

References

  1. 1.
    Telecommunication standardization sector of ITU: Recommendation ITU-T H.265 — International Standard ISO/IEC 23008-2. International Telecommunication Union, Geneva (2015)Google Scholar
  2. 2.
    Bossen, F., Flynn, D., Bross, B., Suhring, K.: HEVC complexity and implementation analysis. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1685–1696 (2012).  https://doi.org/10.1109/TCSVT.2012.2221255CrossRefGoogle Scholar
  3. 3.
    Budagavi, M., Fuldseth, A., Bjøntegaard, G., Sze, V., Sadafale, M.: Core transform design in the high efficiency video coding (HEVC) standard. IEEE J. Sel. Top. Sign. Proces. 7(6), 1029–1041 (2013).  https://doi.org/10.1109/JSTSP.2013.2270429CrossRefGoogle Scholar
  4. 4.
    Tikekar, M., Huang, C.-T., Juvekar, C., Chandrakasan, A.: Core transform property for practical throughput hardware design. Paper Presented at the 7th Meeting of the Joint Collaborative Team on Video Coding (JCT-VC), Geneva, 21–30 November 2011Google Scholar
  5. 5.
    Fuldseth, A., Bjøntegaard, G., Sze, V., Budagavi, M.: Core transform design for HEVC. Paper Presented at the 7th Meeting of the Joint Collaborative Team on Video Coding (JCT-VC), Geneva, 21–30 November 2011Google Scholar
  6. 6.
    Zhao, W., Onoye, T., Song, T.: High-performance multiplierless transform architecture for HEVC. In: IEEE International Symposium on Circuits and Systems, Beijing, pp. 1668–1671. IEEE (2013).  https://doi.org/10.1109/ISCAS.2013.6572184
  7. 7.
    Meher, P.K., Park, S.Y., Mohanty, B.K., Lim, K.S., Yeo, S.: Efficient integer DCT architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 24(1), 168–178 (2014).  https://doi.org/10.1109/TCSVT.2013.2276862CrossRefGoogle Scholar
  8. 8.
    Chatterjee, S., Sarawadekar, K.P.: A low cost, constant throughput and reusable 8X8 DCT architecture for HEVC. In: 59th International Midwest Symposium on Circuits and Systems, Abu Dhabi, pp. 1–4. IEEE (2016).  https://doi.org/10.1109/MWSCAS.2016.7869994
  9. 9.
    Bolaños-Jojoa, J.D., Velasco-Medina, J.: Efficient hardware design of N-point 1D-DCT for HEVC. In: 20th Symposium on Signal Processing, Images and Computer Vision, Bogota, pp. 1–6. IEEE (2015).  https://doi.org/10.1109/STSIVA.2015.7330449
  10. 10.
    Abdelrasoul, M., Sayed, M.S., Goulart, V.: Scalable integer DCT architecture for HEVC encoder. In: IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, pp. 314–318. IEEE (2016).  https://doi.org/10.1109/ISVLSI.2016.98
  11. 11.
    Sjövall, P., Viitamäki, V., Vanne, J., Hämäläinen, T.D.: High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. In: IEEE International Conference on Acoustics, Speech and Signal Processing, New Orleans, pp. 1547–1551. IEEE (2017).  https://doi.org/10.1109/ICASSP.2017.7952416
  12. 12.
    Arayacheeppreecha, P., Pumrin, S., Supmonchai, B.: Flexible input transform architecture for HEVC encoder on FPGA. In: 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, Hua Hin, pp. 1–6. IEEE (2015).  https://doi.org/10.1109/ECTICon.2015.7206947
  13. 13.
    Abdelrasoul, M., Sayed, M.S., Goulart, V.: Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding. IET Circuits Devices Syst. 11(4), 381–387 (2017).  https://doi.org/10.1049/iet-cds.2016.0423CrossRefGoogle Scholar
  14. 14.
    Bjøntegaard, G.: Calculation of average PSNR differences between RD-curves. Paper Presented at the 16th Meeting of the Video Coding Experts Group (VCEG), Austin, 2–4 April 2001Google Scholar
  15. 15.
    Renda, G., Masera, M., Martina, M., Masera, G.: Approximate Arai DCT architecture for HEVC. In: New Generation of CAS, Genova, pp. 133–136. IEEE (2017).  https://doi.org/10.1109/NGCAS.2017.38
  16. 16.
    Tummeltshammer, P., Hoe, J.C., Puschel, M.: Time-multiplexed multiple-constant multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), 1551–1563 (2007).  https://doi.org/10.1109/TCAD.2007.893549CrossRefGoogle Scholar
  17. 17.
    Spiral Project: Multiplexed Multiplier Block Generator. http://spiral.net/hardware/mmcm.html. Accessed 10 Dec 2018
  18. 18.
    Hong, L., Weifeng, H., Zhu, H., Mao, Z.: A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. In: 56th International Midwest Symposium on Circuits and Systems, Columbus, pp. 1290–1293. IEEE (2013).  https://doi.org/10.1109/MWSCAS.2013.6674891

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.HPC Architecture and Application Research Center, Faculty of Electrical Engineering and ComputingUniversity of ZagrebZagrebCroatia

Personalised recommendations