An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator

  • Mate CobrnicEmail author
  • Alen Duspara
  • Leon Dragic
  • Igor Piljic
  • Hrvoje Mlinaric
  • Mario Kovac
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12043)


In this paper is presented an area efficient reusable architecture for integer one dimensional Discrete Cosine Transform (1D DCT) with adjustable transform sizes in High Efficiency Video Coding (HEVC). Optimization is based on exploiting of symmetry and subset properties of the transform matrix. The proposed multiply-accumulate architecture is fully pipelined and applicable for all transform sizes. It provides the interface over which the processing system can control the datapath of the transform process and the synchronization channel that enables the system to receive the feedback information about utilization from the device. An intuitive line approach for calculating transform coefficients for all transform sizes was used instead of the commonly applied recursive decomposition approach. This approach simplifies disabling of lines that are not employed for a particular transform size. The proposed architecture is implemented on the FPGA platform, can operate at 407,5 MHz, achieves throughput of 815 Msps and can support encoding of a 4K UHD@30 fps video sequence in real time.


Integer Discrete Cosine Transform (DCT) High Efficiency Video Coding (HEVC) Field-Programmable Gate Array (FPGA) Pipelined architecture 



The work presented in this paper has been partially funded by the European Processor Initiative project that has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 826647.


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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.HPC Architecture and Application Research Center, Faculty of Electrical Engineering and ComputingUniversity of ZagrebZagrebCroatia

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