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DCSynth: Guided Reactive Synthesis with Soft Requirements

  • Amol WakankarEmail author
  • Paritosh K. Pandya
  • Raj Mohan Matteplackel
Conference paper
  • 30 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12031)

Abstract

In this paper, we propose a technique for guided synthesis of a controller from regular requirements which are specified using an interval temporal logic QDDC . We find that QDDC is well suited for guided synthesis due to its superiority in dealing with both qualitative and quantitative specifications. Our framework allows specification consisting of both hard and soft requirements as QDDC formulas. We have developed a method and a tool DCSynth, which computes a controller that invariantly satisfies the hard requirement and it H-optimally meets the soft requirement. Soft requirements can be used to specify quality attributes. The proposed technique is also useful in dealing with conflicting (i.e. unrealizable) requirements by making some of them as soft requirements. Case studies are carried out to demonstrate the effectiveness of the soft requirement guided synthesis in obtaining high quality controllers. The quality of the synthesized controllers is compared by measuring both the guaranteed as well as the expected case behaviour of the controlled system. Tool DCSynth facilitates such comparison.

References

  1. 1.
    Bellman, R.E.: Dynamic Programming. Princeton University Press, Princeton (1957)zbMATHGoogle Scholar
  2. 2.
    Bloem, R., et al.: Synthesizing robust systems. Acta Inf. 51(3–4), 193–220 (2014).  https://doi.org/10.1007/s00236-013-0191-5MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Bloem, R., Chatterjee, K., Henzinger, T.A., Jobstmann, B.: Better quality in synthesis through quantitative objectives. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 140–156. Springer, Heidelberg (2009).  https://doi.org/10.1007/978-3-642-02658-4_14CrossRefGoogle Scholar
  4. 4.
    Bohy, A., Bruyère, V., Filiot, E., Jin, N., Raskin, J.-F.: Acacia+, a tool for LTL synthesis. In: Madhusudan, P., Seshia, S.A. (eds.) CAV 2012. LNCS, vol. 7358, pp. 652–657. Springer, Heidelberg (2012).  https://doi.org/10.1007/978-3-642-31424-7_45CrossRefGoogle Scholar
  5. 5.
    Bouyer, P., Markey, N., Randour, M., Larsen, K.G., Laursen, S.: Average-energy games. Acta Informatica 55(2), 91–127 (2018).  https://doi.org/10.1007/s00236-016-0274-1MathSciNetCrossRefzbMATHGoogle Scholar
  6. 6.
    Chakravorty, G., Pandya, P.K.: Digitizing interval duration logic. In: Hunt, W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 167–179. Springer, Heidelberg (2003).  https://doi.org/10.1007/978-3-540-45069-6_17CrossRefGoogle Scholar
  7. 7.
    Zhou, C., Hansen, M.R.: Duration Calculus - A Formal Approach to Real-Time Systems. Monographs in Theoretical Computer Science. An EATCS Series. Springer, Heidelberg (2004).  https://doi.org/10.1007/978-3-662-06784-0CrossRefzbMATHGoogle Scholar
  8. 8.
    Zhou, C., Hoare, C.A.R., Ravn, A.P.: A calculus of durations. Inf. Process. Lett. 40(5), 269–276 (1991).  https://doi.org/10.1016/0020-0190(91)90122-XMathSciNetCrossRefzbMATHGoogle Scholar
  9. 9.
    Ding, X.C., Lazar, M., Belta, C.: LTL receding horizon control for finite deterministic systems. Automatica 50(2), 399–408 (2014).  https://doi.org/10.1016/j.automatica.2013.11.030MathSciNetCrossRefzbMATHGoogle Scholar
  10. 10.
    Ehlers, R., Lafortune, S., Tripakis, S., Vardi, M.Y.: Supervisory control and reactive synthesis: a comparative introduction. Discrete Event Dyn. Syst. 27(2), 209–260 (2017).  https://doi.org/10.1007/s10626-015-0223-0MathSciNetCrossRefzbMATHGoogle Scholar
  11. 11.
    Faymonville, P., Finkbeiner, B., Tentrup, L.: BoSy: an experimentation framework for bounded synthesis. In: Majumdar, R., Kunčak, V. (eds.) CAV 2017. LNCS, vol. 10427, pp. 325–332. Springer, Cham (2017).  https://doi.org/10.1007/978-3-319-63390-9_17CrossRefGoogle Scholar
  12. 12.
    Grädel, E., Thomas, W., Wilke, T. (eds.): Automata Logics, and Infinite Games. LNCS, vol. 2500. Springer, Heidelberg (2002).  https://doi.org/10.1007/3-540-36387-4CrossRefzbMATHGoogle Scholar
  13. 13.
    IEC: IEC 62531:2012(e) (IEEE std 1850–2010): Standard for property specification language (PSL). IEC 62531:2012(E) (IEEE Std 1850–2010), pp. 1–184, June 2012.  https://doi.org/10.1109/IEEESTD.2012.6228486
  14. 14.
    Jacobs, S., et al.: The 4th reactive synthesis competition (SYNTCOMP 2017): benchmarks, participants & results. CoRR abs/1711.11439 (2017). http://arxiv.org/abs/1711.11439
  15. 15.
    Katoen, J., Zapreev, I.S., Hahn, E.M., Hermanns, H., Jansen, D.N.: The INS and outs of the probabilistic model checker MRMC. Perform. Eval. 68, 89–220 (2011).  https://doi.org/10.1016/j.peva.2010.04.001CrossRefGoogle Scholar
  16. 16.
    Klarlund, N., Møller, A., Schwartzbach, M.I.: MONA implementation secrets 2088, 182–194 (2001).  https://doi.org/10.1007/3-540-44674-5_15CrossRefGoogle Scholar
  17. 17.
    Krishna, S.N., Pandya, P.K.: Modal strength reduction in quantified discrete duration calculus. In: Sarukkai, S., Sen, S. (eds.) FSTTCS 2005. LNCS, vol. 3821, pp. 444–456. Springer, Heidelberg (2005).  https://doi.org/10.1007/11590156_36CrossRefGoogle Scholar
  18. 18.
    Lafortune, S., Rudie, K., Tripakis, S.: Thirty years of the ramadge-wonham theory of supervisory control: a retrospective and future perspectives [conference reports]. IEEE Control Syst. Mag. 38(4), 111–112 (2018).  https://doi.org/10.1109/MCS.2018.2830083CrossRefGoogle Scholar
  19. 19.
    Matteplackel, R.M., Pandya, P.K., Wakankar, A.: Formalizing timing diagram requirements in discrete duration calculus. In: Cimatti, A., Sirjani, M. (eds.) SEFM 2017. LNCS, vol. 10469, pp. 253–268. Springer, Cham (2017).  https://doi.org/10.1007/978-3-319-66197-1_16CrossRefGoogle Scholar
  20. 20.
    Pandya, P.K.: Model checking CTL*[DC]. In: Margaria, T., Yi, W. (eds.) TACAS 2001. LNCS, vol. 2031, pp. 559–573. Springer, Heidelberg (2001).  https://doi.org/10.1007/3-540-45319-9_38CrossRefGoogle Scholar
  21. 21.
    Pandya, P.K.: Specifying and deciding quantified discrete-time duration calculus formulae using DCVALID. In: RTTOOLS (affiliated with CONCUR 2001) (2001)Google Scholar
  22. 22.
    Pandya, P.K.: The saga of synchronous bus arbiter: on model checking quantitative timing properties of synchronous programs. Electr. Notes Theor. Comput. Sci. 65(5), 110–124 (2002).  https://doi.org/10.1016/S1571-0661(05)80445-1CrossRefGoogle Scholar
  23. 23.
    Pandya, P.K., Wakankar, A.: Specification and reactive synthesis of robust controllers. CoRR abs/1905.11157 (2019). http://arxiv.org/abs/1905.11157
  24. 24.
    Puterman, M.L.: Markov Decision Processes: Discrete Stochastic Dynamic Programming, 1st edn. Wiley, Hoboken (1994)CrossRefGoogle Scholar
  25. 25.
    Ramadge, P., Wonham, W.: Supervisory control of a class of discrete event processes. SIAM J. Control Optim. 25(1), 206–230 (1987).  https://doi.org/10.1137/0325013MathSciNetCrossRefzbMATHGoogle Scholar
  26. 26.
    Ramadge, P., Wonham, W.: The control of discrete event systems. Proc. IEEE 77, 81–98 (1989).  https://doi.org/10.1109/5.21072CrossRefGoogle Scholar
  27. 27.
    Raman, V., Donzé, A., Sadigh, D., Murray, R.M., Seshia, S.A.: Reactive synthesis from signal temporal logic specifications. In: HSCC, HSCC 2015, pp. 239–248. ACM (2015).  https://doi.org/10.1145/2728606.2728628
  28. 28.
    Riedweg, S., Pinchinat, S.: Quantified mu-calculus for control synthesis. In: Rovan, B., Vojtáš, P. (eds.) MFCS 2003. LNCS, vol. 2747, pp. 642–651. Springer, Heidelberg (2003).  https://doi.org/10.1007/978-3-540-45138-9_58CrossRefGoogle Scholar
  29. 29.
    Sharma, B., Pandya, P.K., Chakraborty, S.: Bounded validity checking of interval duration logic. In: Halbwachs, N., Zuck, L.D. (eds.) TACAS 2005. LNCS, vol. 3440, pp. 301–316. Springer, Heidelberg (2005).  https://doi.org/10.1007/978-3-540-31980-1_20CrossRefzbMATHGoogle Scholar
  30. 30.
    Wakankar, A., Pandya, P.K., Matteplackel, R.M.: DCSynth 1.0. TIFR, Mumbai (2018). http://www.tcs.tifr.res.in/~pandya/dcsynth/dcsynth.html
  31. 31.
    Wakankar, A., Pandya, P.K., Matteplackel, R.M.: DCSynth: a tool for guided reactive synthesis with soft requirements, VSTTE 2019. CoRR abs/1903.03991 (2019, in press). http://arxiv.org/abs/1903.03991
  32. 32.
    Wongpiromsarn, T., Topcu, U., Murray, R.M.: Receding horizon temporal logic planning. IEEE Trans. Automat. Contr. 57(11), 2817–2830 (2012).  https://doi.org/10.1109/TAC.2012.2195811MathSciNetCrossRefzbMATHGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Amol Wakankar
    • 1
    • 2
    Email author
  • Paritosh K. Pandya
    • 3
  • Raj Mohan Matteplackel
    • 3
  1. 1.Homi Bhabha National InstituteMumbaiIndia
  2. 2.Bhabha Atomic Research CentreMumbaiIndia
  3. 3.Tata Institute of Fundamental ResearchMumbaiIndia

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