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IC Camouflaging Optimization and Evaluation

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A Synergistic Framework for Hardware IP Privacy and Integrity Protection

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Abstract

The advancing of reverse engineering techniques has complicated the efforts in intellectual property protection. Proactive methods have been developed recently, among which layout-level IC camouflaging is the leading example. However, existing camouflaging methods are rarely supported by provably secure criteria, which further leads to an overestimation of the security level when countering latest de-camouflaging attacks, e.g., the SAT-based attack. This chapter focuses on evaluating and improving the resilience of IC camouflaging strategies against de-camouflaging attacks. A provably secure camouflaging framework is developed based on a low-overhead camouflaging cell generation strategy and an AND-tree camouflaging strategy. An evaluation framework is also proposed that is capable of empirically evaluating the security of all the camouflaging strategies.

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Notes

  1. 1.

    Although SAT attack for sequential circuits has been proposed recently [11], it requires unbounded model checking to formally guarantee the correctness of the resolved netlist, which can be intractable.

  2. 2.

    We assume there are no combinational loops in the original netlist, which holds for most of the circuits.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

    Meng Li & David Z. Pan

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  1. Meng Li
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  2. David Z. Pan
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Li, M., Pan, D.Z. (2020). IC Camouflaging Optimization and Evaluation. In: A Synergistic Framework for Hardware IP Privacy and Integrity Protection. Springer, Cham. https://doi.org/10.1007/978-3-030-41247-0_3

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  • DOI: https://doi.org/10.1007/978-3-030-41247-0_3

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