Design and Implementation of AES on FPGA for Security of IOT Data

  • Dinesh B. BhoyarEmail author
  • Shelly R. Wankhede
  • Swati K. Modod
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1122)


As we know that the world is been surrounded by the internet and interconnected to it and the different things or we can say the edge devices which helps us to connect to network and communicate to the different alternatives with the surroundings. In this paper we would be discussing about the different algorithms and their and disadvantages and how the advanced standard algorithm is been applied we has an great effect on cryptography and the different process carried out in the encryption and decryption process. In this paper the encryption and the decryption would be given in 128 bit format in hexadecimal, binary or any other format and the key expansion for getting the cipher text. in cryptography their are three classification for the expansion of the key which can be symmetric, asymmetric and the hash function in this paper we have discussed and the symmetric key is been given for both encryption and decryption we know that we are using the 128 bit length which has 10 rounds and the initial round includes the state and the different transformation in the cryptograpy process which is the symmetric key expansion in which the same key is been applied to both encryption and decryption in binary, hexadecimal, etc. As it is lossless operation many applications can be derived using this algorithm as we are using symmetric key block cipher. We are limiting our paper with the 128 bit length of data in verilog language. For encryption and decryption the proposed paper describes the cryptograpy which would be having the fixed size. In this algorithm where we are using the symmetric key block cipher where the key would be given same with respect to encryption. Many applications it can be used as it is lossless operation. We limit our focus on 12b8 bit AES encryption and decryption where coded in VHDL coding. The proposed paper describes the private key cryptosystems which has a key with fixed size.


AES FPGA Key IOT Cloud security VHDL 


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Copyright information

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Dinesh B. Bhoyar
    • 1
    Email author
  • Shelly R. Wankhede
    • 1
  • Swati K. Modod
    • 2
  1. 1.Department of Electronics and Telecommunication EngineeringYeshwantrao Chavan College of EngineeringWanadongri, NagpurIndia
  2. 2.Department of Electronics and Telecommunication EngineeringRajiv Gandhi College of Engineering and TechnologyWanadongri, NagpurIndia

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