Hardware Design of 8 × 8 and 16 × 16 2D Discrete Cosine Transform with N/2 Equations for Image Compression

  • Nikhil C. BichweEmail author
  • Rahul Kumar Chaurasiya
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1122)


The discrete cosine transform (DCT) has remarkable significance in the area of image and video compression due to its energy compaction property. This paper propose a distinct architecture for 8 × 8 and 16 × 16 2D-DCT for compression of images. A method is proposed to reduce the number of equations with the help of high energy compaction property of DCT. In the conventional N point, 1D-DCT requires N number of equations for the transformation, by using high energy compaction property, only N/2 equations are required to perform the task. Proposed architecture reduces the arithmetic complexity. Further, it exhibits low power consumption with less area requirement. The proposed 2D-DCT is synthesized in XC3S700AN and XC6VLX75T devices, and the simulation results are compared with conventional 2D-DCT. The quality of the reconstructed image is evaluated by peak signal to noise ratio (PSNR). The obtained result shows the 75% reduction in the number of pixels required to store the image.


Discrete cosine transform (DCT) Joint photographic experts group (JPEG) Field programmable gate array (FPGA) Peak Signal to Noise Ratio (PSNR) Xilinx 


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© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of Electronics and TelecommunicationNITRaipurIndia
  2. 2.Department of Electronics and Communication EngineeringMNITJaipurIndia

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