Abstract
Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving their performance and utility. The FD-SOI silicon process enables integrated systems that can deliver dramatic improvements in energy efficiency through system integration. This chapter presents the Raven-3 and Raven-4 testchips, fully integrated and fully featured SoCs which achieve energy-efficient operation with low overhead. RISC-V processors allow for innovation and experimentation in the context of a free, open architecture. Integrated switched-capacitor voltage regulators can achieve high conversion efficiency when coupled with adaptive clock generators. Custom SRAM macros operate at low supply voltages, enabling wide voltage scaling. An integrated body-bias generator allows run-time tuning of threshold voltage for improved performance or reduced leakage. Taken together, these innovations showcase the possibilities of FD-SOI technology.
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References
B. Keller, Energy-efficient system design through adaptive voltage scaling. Ph.D. dissertation, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, December 2017
B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtić, B. Keller, S. Bailey, M. Blagojević, P.F. Chiu, H.P. Le, P.H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanović, B. Nikolić, A RISC-V vector processor with simultaneous-switching switched-capacitor DC-DC converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4), 930–942 (2016)
P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, N. Planes, J. Le Coz, O. Thomas, S. Engels, G. Cesana, R. Wilson, P. Urard, Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2013), pp. 424–425
B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojević, S. Bailey, P.F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, B. Nikolić, A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI. IEEE J. Solid State Circuits 52(7), 1863–1875 (2017)
B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojević, J. Kwak, A. Puggelli, S. Bailey, P.F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, B. Nikolić, Sub-microsecond adaptive voltage scaling in a 28 nm FD-SOI processor SoC, in Proceedings of the European Solid-State Circuits Conference, September (2016), pp. 269–272
The RISC-V ISA [Online]. Available http://riscv.org
K. Asanović, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar, B. Keller, D. Kim, J. Koenig, Y. Lee, E. Love, M. Maas, A. Magyar, H. Mao, M. Moreto, A. Ou, D.A. Patterson, B. Richards, C. Schmidt, S. Twigg, H. Vo, A. Waterman, The rocket chip generator. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. Technical Report UCB/EECS-2016-17 (2016)
Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanovic, K. Asanović, A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators, in Proceedings of the European Solid-State Circuits Conference, September (2014), pp. 199–202
R.M. Russell, The CRAY-1 computer system. Commun. ACM 21(1), 63–72 (1978)
N. Planes, O. Weber, V. Barral, S. Haendler, D. Noblet, D. Croain, M. Bocat, P. Sassoulas, X. Federspiel, A. Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, D. Petit, D. Golanski, C. Fenouillet-Beranger, N. Guillot, M. Rafik, V. Huard, S. Puget, X. Montagner, M.A. Jaud, O. Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, M. Haond, 28nm FDSOI technology platform for high-speed low-voltage digital applications, in Proceedings of the IEEE Symposium on VLSI Technology, June (2012), pp. 133–134
B. Zimmer, O. Thomas, S.O. Toh, T. Vincent, K. Asanović, B. Nikolić, Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM, in Proceedings of the IEEE European Solid-State Device Research Conference, September (2014), pp. 98–101
S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J.-M. Daveau, C. Bottoni, D. Bol, J. De-Vos, D. Zamora, B. Coeffic, D. Soussan, D. Croain, M. Naceur, P. Schamberger, P. Roche, D. Sylvester, A 0.33V/-40C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2015), pp. 150–151
R. Jain, S. Kim, V. Vaidya, J. Tschanz, K. Ravichandran, V. De, Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm tri-gate CMOS, in Proceedings of the IEEE Custom Integrated Circuits Conference, September (2014), pp. 1–4
J. Jiang, Y. Lu, W.H. Ki, U. Seng-Pan, R.P. Martins, A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2017), pp. 344–345
S. Kim, Y.-C. Shih, K. Mazumdar, R. Jain, J. Ryan, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De, Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2015), pp. 154–155
M.K. Song, L. Chen, J. Sankman, S. Terry, D. Ma, A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2015), pp. 302–304
C.K. Teh, A. Suzuki, A 2-output step-up/step-down switched-capacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V input voltage range, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, January (2016), pp. 222–223
T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brundli, P. Buchmann, P.A. Francese, A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2014), pp. 90–91
H.-P. Le, S. Sanders, E. Alon, Design techniques for fully integrated switched-capacitor DC-DC converters. IEEE J. Solid State Circuits 46(9), 2120–2131 (2011)
G.V. Piqué, A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOS, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February (2012), pp. 98–100
R. Jevtić, H.P. Le, M. Blagojević, S. Bailey, K. Asanović, E. Alon, B. Nikolić, Per-core DVFS with switched-capacitor converters for energy efficiency in manycore processors. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(4), 723–730 (2015)
J.W. Tschanz, J.T. Kao, S.G. Narendra, R. Nair, D.A. Antoniadis, A.P. Chandrakasan, V. De, Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J. Solid State Circuits 37(11), 1396–1402 (2002)
M. Blagojević, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, B. Nikolić, A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI, in Proceedings of the Symposium on VLSI Circuits, June (2016), pp. 61–62
Y. Tsukikawa, T. Kajimoto, Y. Okasaka, H. Miyamoto, H. Ozaki, An efficient back-bias generator with hybrid pumping circuit for 1.5 v drams, in Proceedings of the Symposium on VLSI Circuits, May (1993), pp. 85–86
J. Kwak, B. Nikolić, A self-adjustable clock generator with wide dynamic range in 28 nm FDSOI. IEEE J. Solid State Circuits 51(10), 2368–2379 (2016)
D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T.D. Gilio, C. Lecocq, T. Roy, A. Chhabra, C. Grover, O. Minez, J. Uginet, G. Durieu, C. Adobati, D. Casalotto, F. Nyer, P. Menut, A. Cathelin, I. Vongsavady, P. Magarshack, A 3 GHz dual core processor ARM Cortex-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization. IEEE J. Solid State Circuits 49(4), 812–826 (2014)
M. Cochet, A. Puggelli, B. Keller, B. Zimmer, M. Blagojević, S. Clerc, P. Roche, J.L. Autran, B. Nikoli, On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC, in Proceedings of the IEEE Asian Solid-State Circuits Conference, November (2016), pp. 125–128
Acknowledgements
Fabrication of the Raven-3 and Raven-4 testchips was donated by STMicroelectronics. The research presented in this chapter was supported by the Berkeley Wireless Research Center, the Berkeley ASPIRE Lab, DARPA PERFECT Award Number HR0011-12-2-0016, Intel ARO, AMD, SRC/TxACE, Marie Curie FP7, the NSF GRFP, and the NVIDIA Fellowship.
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Keller, B. et al. (2020). System Integration of RISC-V Processors with FD-SOI. In: Clerc, S., Di Gilio, T., Cathelin, A. (eds) The Fourth Terminal. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-39496-7_11
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