Advertisement

Low Power BCH Decoder Using Verification Algorithm and Two-Step Parallel Chien Search Architecture

  • Noha K. SheblEmail author
  • Saleh M. Eisa
  • Hanady H. Issa
  • Khaled A. ShehataEmail author
Conference paper
  • 88 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1129)

Abstract

Bose-Chaudhuri-Hocquenghem (BCH) code is normally utilized in communication systems in order to enhance its reliability. The main computational complexity and high power consumption stages in BCH come from its two main stages, the key equation solving (KES) and Chien search (CS). This paper presents two different algorithms to reduce the computational process and hence reduce the total power consumption. These algorithms are the verification algorithm and the two-step parallel CS architecture which are utilized in KES and CS stages, respectively. The whole proposed system is implemented using LABVIEW tools from NI. The results show that the proposed BCH algorithm provides an enhanced performance when compared to the conventional one.

Keywords

Bose-Chaudhuri-Hocquenghem (BCH) codes Key equation solving (KES) Chien search (CS) BM LABVIEW 

References

  1. 1.
    Moreira, J.C., Farrell, P.G.: Essentials of Error-Control Coding. Wiley, Hoboken (2006)Google Scholar
  2. 2.
    Sklar, B.: Digital Communications, Fundamentals and Applications, 2nd edn. Prentice-Hall, Upper Saddle River (1988)Google Scholar
  3. 3.
    Wu, Y.: Low power decoding of BCH codes. In: Proceedings of the IEEE ISCAS, pp. II-369–II-372, May 2004Google Scholar
  4. 4.
    Lee, K., Lim, S., Kim, J.: Low-cost, low-power and high throughput BCH decoder for NAND flash memory. In: Proceedings of the IEEE ISCAS, pp. 413–415, May 2012Google Scholar
  5. 5.
    Wong, S., Chen, C., Wu, Q.M.: Low power Chien search for BCH decoder using RT-level power management. IEEE Trans. Very Large Scale Integr. Syst. 19(2), 338–341 (2011)CrossRefGoogle Scholar
  6. 6.
    Yoo, H., Lee, Y., Park, I.: Low-power parallel Chien search architecture using a two-step approach. IEEE Trans. Circ. Syst. II: Express Briefs 63(3), 269–273 (2016)CrossRefGoogle Scholar
  7. 7.
    Zheng, N., Mazumder, P.: An efficient eligible error locator polynomial searching algorithm and hardware architecture for one-pass chase bch codes decoding. IEEE Trans. Circ. Syst. II: Express Briefs (2016).  https://doi.org/10.1109/TCSII.2016.2581587CrossRefGoogle Scholar
  8. 8.
    Shebl, N.K., Eisa, S.M., Isaa, H.H., Shehata, K.A.: A low power BCH based on error locator polynomial searching algorithm and two step parallel Chien search algorithm. In: 3rd International Conference on Advanced Technology & Applied Sciences (ICaTAS), Malaysia-Japan International Institute of technology, Malaysia (2018)Google Scholar
  9. 9.
    Lin, S., Costello, D.J.: Error Control Coding, Fundamentals and Applications. Prentice-Hall, Inc., Englewood Cliffs (1983)Google Scholar
  10. 10.
    Wicker, S.B.: Error Control Systems for Digital Communication and Storage. Prentice-Hall, Englewood Cliffs (1994)zbMATHGoogle Scholar
  11. 11.
    Lee, Y., Yoo, H., Park, I.-C.: High-throughput and low-complexity BCH decoding architecture for solid-state drives. IEEE Trans. Very Large Scale Integr. Syst. 22(5), 1183–1187 (2014)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of Electronics and CommunicationArab Academy for Science and TechnologyCairoEgypt

Personalised recommendations