Design of a SpaceFibre High-Speed Satellite Interface ASIC

  • Pietro NannipieriEmail author
  • Gianmarco Dinelli
  • Luca Dello Sterpaio
  • Antonino Marino
  • Luca Fanucci
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 627)


In the last few years, data rate requirement in on-board data handling for space missions has continuously grown, due to the presence of high resolution instruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 6.25 Gbit/s per communication lane (up to 16 communication lanes). This work proposes the design of a SpaceFibre interface Application Specific Integrated Circuit. The block diagram of the system is presented, together with results in terms of area occupation and power consumption (excluding serialiser-deserialiser circuitry) after the synthesis on a 65 nm CMOS technology.


SpaceFibre CODEC 65 nm ASIC Logic synthesis On-board data-handling Satellite High-speed 



IngeniArs SpaceFibre technologies have been developed in the framework of the project SIMPLE (Spacefibre IMPLementation design & test Equipment). This project has received funding from the European Unions Horizon 2020 research and innovation programme under Grant Agreement No. 757038.


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Pietro Nannipieri
    • 1
    Email author
  • Gianmarco Dinelli
    • 1
  • Luca Dello Sterpaio
    • 1
  • Antonino Marino
    • 1
  • Luca Fanucci
    • 1
  1. 1.Department of Information EngineeringUniversity of PisaPisaItaly

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