Advertisement

Design of a SpaceFibre High-Speed Satellite Interface ASIC

  • Pietro NannipieriEmail author
  • Gianmarco Dinelli
  • Luca Dello Sterpaio
  • Antonino Marino
  • Luca Fanucci
Conference paper
  • 10 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 627)

Abstract

In the last few years, data rate requirement in on-board data handling for space missions has continuously grown, due to the presence of high resolution instruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 6.25 Gbit/s per communication lane (up to 16 communication lanes). This work proposes the design of a SpaceFibre interface Application Specific Integrated Circuit. The block diagram of the system is presented, together with results in terms of area occupation and power consumption (excluding serialiser-deserialiser circuitry) after the synthesis on a 65 nm CMOS technology.

Keywords

SpaceFibre CODEC 65 nm ASIC Logic synthesis On-board data-handling Satellite High-speed 

Notes

Acknowledgements

IngeniArs SpaceFibre technologies have been developed in the framework of the project SIMPLE (Spacefibre IMPLementation design & test Equipment). This project has received funding from the European Unions Horizon 2020 research and innovation programme under Grant Agreement No. 757038.

References

  1. 1.
    Space engineering—SpaceFibre—very high-speed serial link. European Cooperation for Space Standardisation, ECSS-E-ST-50-11C, May 2019Google Scholar
  2. 2.
    Rivera JP, Sabater N, Tenjo C, Vicen J, Alonso L, Moreno J (2014) Synthetic scene simulator for hyperspectral spaceborne passive optical sensors. Application to ESA’s FLEX/sentinel-3 tandem mission. In: Proceeding of the 2014 6th workshop on hyperspectral image and signal processing: evolution in remote sensing (WHISPERS), Lausanne, SW, 24–27 June 2014Google Scholar
  3. 3.
    Toan TL et al (2018) The biomass mission: objectives and requirements. In: Proceeding of 2018 IEEE international geoscience and remote sensing symposium, Valencia, SP, 22–27 Jul 2018Google Scholar
  4. 4.
    Parkes S et al (2015) SpaceFibre: multi-gigabit/s interconnect for spacecraft on-board data handling. In: Proceeding of the IEEE aerospace conference, Big Sky, MT, USA, 2015, pp 1–8Google Scholar
  5. 5.
    Nannipieri P, Dinelli G, Davalle D, Fanucci L (2018) A SpaceFibre multi lane CODEC system on a chip: enabling technology for low cost satellite EGSE. In: 2018 14th conference on Ph.D. research in microelectronics and electronics (PRIME), Prague, 2018, pp 173–176Google Scholar
  6. 6.
    Siegle F, Habinc S, Both J (2016) SpaceFibre Port IP Core (GRSPFI): SpaceFibre, poster paper. In: Proceedings of the 7th international spacewire conference, Yokohama, Japan, 2016, pp 1–5Google Scholar
  7. 7.
    Leoni A, Nannipieri P, Fanucci L (2019) VHDL design of a SpaceFibre routing switch. IEICE Trans Fundam Electron Commun Comput Sci E102A(5):729–731Google Scholar
  8. 8.
    Nannipieri P, Davalle D, Fanucci L (2018) A novel parallel 8B/10B encoder: architecture and comparison with classical solution. IEICE Trans Fundam Electron Commun Comput Sci E101A(7):1120–1122Google Scholar
  9. 9.
    Villafranca AG, Ferrer A, McLaren D, McClements C, Parkes S (2015) VHiSSI: experimental SpaceFibre ASIC. In: European Space Agency (Special Publication) ESA SP, SP-732Google Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Pietro Nannipieri
    • 1
    Email author
  • Gianmarco Dinelli
    • 1
  • Luca Dello Sterpaio
    • 1
  • Antonino Marino
    • 1
  • Luca Fanucci
    • 1
  1. 1.Department of Information EngineeringUniversity of PisaPisaItaly

Personalised recommendations