FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction

  • Dario RussoEmail author
  • Stefano Ricci
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 627)


Frame jitter occurs when the delay between a trigger and the start of a signal acquisition or signal generation is different among subsequence data frames. Test bench waveform signal generators features low frame jitter (e.g. 400 ps rms), but this performance is still insufficient for the instrument to be used in sensitive applications like Doppler velocimetry. In this work a circuit is presented that synchronizes on-the-fly an internal clock to every occurrence of an external trigger. It is implemented in a Field Programmable Gate Array (FPGA) and features a frame jitter lower than 100 ps rms.


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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Information Engineering DepartmentUniversity of FlorenceFlorenceItaly

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