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Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application

  • Sisir Kumar JenaEmail author
  • Santosh Biswas
  • Jatindra Kumar Deka
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11942)

Abstract

Approximate computing techniques emerged as a novel design paradigm that utilizes the error-resilience property of many applications and helps in reducing the power and area consumption with an expense of loss in accuracy of the result. In this paper, we introduce Significance-based gate-level pruning (SGLP) technique to design an approximate adder circuit whose accuracy can be controlled using an Error-Threshold provided by the application user. All previous method are nonsystematic and conceptually different from each other. Those methods can either apply to a chain-based adder (adders made up of a chain of full adders, e.g., Ripple Carry Adder) or unchain-based adder (e.g., Kogge-Stone Adder) but not both. SGLP follows a systematic approach to generate an approximate version of a Full Adder which is later used to produce multi-bit adder. By using the SGLP method, we can also realize an approximate variant of an unchained adder. This characteristic makes the SGLP more superior than the previous methods. To check the quality and reliability, we have tested our approach using a DCT architecture for image processing particularly image compression and found that our result is acceptable to human perception-behavior on image clarity.

Keywords

Approximate computing Approximate circuit design Approximate adder Low power design Gate-level pruning 

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of CSEIndian Institute of Technology GuwahatiGuwahatiIndia

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