Enabling Fast and Highly Effective FPGA Design Process Using the CAPI SNAP Framework

  • Alexandre CastellaneEmail author
  • Bruno MesnetEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11887)


The CAPI SNAP (Storage, Network, and Analytics Programming) is an open source framework which enables C/C++ as well as FPGA programmers to quickly create FPGA-based accelerated computing that works on server host data, as well as data from storage, flash, Ethernet, or other connected resources. The SNAP framework is based on the IBM Coherent Accelerator Processor Interface (CAPI). From POWER8 with CAPI1.0, to POWER9 with CAPI2.0 and OpenCAPI, programmers can have access to a very simple framework to develop accelerated applications using high speed and very low latency interfaces to access an external FPGA. With SNAP, no specific hardware skill is required to port or develop an application and then accelerate it. Even more, a cloud environment is being offered as a cost effective, ready-to-use environment for a first-time right experience as well as a deeper development so that it can be achieved with very little investment.


Innovative hardware/software co-design Processor architecture Chip multiprocessors Custom and reconfigurable logic Solutions for parallel programming challenges Parallel programming languages Libraries Models and notations Alternative and specialized parallel operating systems and runtime systems 


  1. 1.
    Peltenburg, J., van Straten, J., Brobbel, M., Hofstee, H.P., Al-Ars, Z.: Supporting columnar in-memory formats on FPGA: the hardware design of fletcher for apache arrow. In: Hochberger, C., Nelson, B., Koch, A., Woods, R., Diniz, P. (eds.) ARC 2019. LNCS, vol. 11444, pp. 32–47. Springer, Cham (2019). Scholar
  2. 2.
  3. 3.
    Diamantopoulos, D., et al.: Energy efficient coherent transprecision accelerators—the bidirectional long short-term memory neural network case (2018)
  4. 4.
    Choi, Y.K., et al.: A quantitative analysis on microarchitectures of modern CPU-FPGA platforms. In: 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE (2016)Google Scholar
  5. 5.
  6. 6.
    Putnam, A., et al.: A reconfigurable fabric for accelerating large-scale datacenter services. In: ISCA (2014)Google Scholar
  7. 7.
    Intel, Intel quickpath interconnect fpga core cache interface specificationGoogle Scholar
  8. 8.
    Brewer, T.M.: Instruction set innovations for the convey hc-1 computer. IEEE Micro 2, 70–79 (2010)CrossRefGoogle Scholar
  9. 9.
    Stuecheli, J., et al.: CAPI: a coherent accelerator processor interface. IBM J. Res. Dev. 59(1), 7:1–7:7 (2015)CrossRefGoogle Scholar
  10. 10.
  11. 11.
    Very small, readable implementation of the SHA3 hash function.
  12. 12.
  13. 13.
    Alpha-Data ADM-PCIE-KU3 board information.
  14. 14.

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.OpenCAPI and CAPI SNAP Enablement IBM FranceMontpellierFrance

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