Design of High Performance FinFET SRAM Cell for Write Operation

  • T. G. Sargunam
  • C. M. R. PrabhuEmail author
  • Ajay Kumar Singh
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 35)


A novel FinFET based SRAM cell is proposed to reduce the dynamic power consumption during write mode in this research work. The proposed High Performance FinFET SRAM (HPFS) cell consists of 8-Transistors instead of 6-Transistors as in conventional SRAM cell. The extra two transistors are used to reduce the write power during transition. The proposed circuit is simulated for Microwind EDA tool. The results of HPFS cell is compared with conventional SRAM cells. From the simulated results, it has been observed that the suggested HPFS cell consumes lower power and provides lower access delay compared to other cells.


FinFET High performance Low power SRAM cell Power consumption Low power and access delay 


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • T. G. Sargunam
    • 1
  • C. M. R. Prabhu
    • 2
    Email author
  • Ajay Kumar Singh
    • 2
  1. 1.School of Science and EngineeringManipal International UniversityNilaiMalaysia
  2. 2.Faculty of Engineering and TechnologyMultimedia UniversityMelakaMalaysia

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