System-on-Chip Security Vulnerabilities

  • Farimah Farahmandi
  • Yuanwen Huang
  • Prabhat Mishra


Modern System-on-Chip (SoC) designs contain several highly sensitive assets such as encryption keys, device configurations, and on-device protected data that are responsible for keeping our personal, financial, and intimate physiological information safe and secure. These assets should be protected from any unauthorized access. Attacks on hardware can harm human life and environment by causing damages to critical infrastructure, violating personal privacy, or undermining the credibility of a business. Trust establishment in semiconductor designs has become a major challenge for design houses since several countries and companies are involved during different stages of a design life cycle. Vulnerabilities can be introduced during different design stages (such as defining specification, implementing designs at different abstraction levels, layout extraction, or during manufacturing). In this chapter, we review the modern semiconductor supply chain and provide an overview of SoC security vulnerabilities and their sources.


  1. 1.
    S. Bhunia, M.S. Hsiao, M. Banga, S. Narasimhan, Hardware Trojan attacks: threat analysis and countermeasures. Proc. IEEE 102(8), 1229–1247 (2014)CrossRefGoogle Scholar
  2. 2.
  3. 3.
    R.S. Chakraborty, F. Wolf, C. Papachristou, S. Bhunia, MERO: a statistical approach for hardware Trojan detection, in International Workshop on Cryptographic Hardware and Embedded Systems (CHES’09) (2009), pp. 369–410Google Scholar
  4. 4.
    Common Weakness Enumeration,
  5. 5.
    DARPA System Security Integrated Through Hardware and Firmware (SSITH),
  6. 6.
    H. Kaeslin, Top-down Digital VLSI Design: From Architectures to Gate-level Circuits and FPGAs (Morgan Kaufmann, Waltham, 2014)Google Scholar
  7. 7.
    P.C. Kocher, J. Jaffe, B. Jun, Differential power analysis, in Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology, Series CRYPTO ’99, London, UK (Springer, London, 1999), pp. 388–397. [Online]. Available: CrossRefGoogle Scholar
  8. 8.
    C. Li, J. Gaudiot, Online detection of spectre attacks using microarchitectural traces from performance counters, in 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Lyon, France (2018), pp. 25–28Google Scholar
  9. 9.
    M. Lipp, M. Schwarz, D. Gruss, T. Prescher, W. Haas, A. Fogh, J. Horn, S. Mangard, P. Kocher, D. Genkin, Y. Yarom, M. Hamburg, Meltdown: reading kernel memory from user space, in 27th Security Symposium (USENIX Security) (2018), pp. 973–990Google Scholar
  10. 10.
    A. Nahiyan, K. Xiao, K. Yang, Y. Jin, D. Forte, M. Tehranipoor, AVFSM a framework for identifying and mitigating vulnerabilities in FSMs, in 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2016), pp. 1–6Google Scholar
  11. 11.
    A. Nahiyan, F. Farahmandi, P. Mishra, D. Forte, M. Tehranipoor, Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6), 1003–1016 (2019)CrossRefGoogle Scholar
  12. 12.
    S. Ray, E. Peeters, M.M. Tehranipoor, S. Bhunia, System-on-chip platform security assurance: architecture and validation. Proc. IEEE 106(1), 21–37 (2018)CrossRefGoogle Scholar
  13. 13.
    B. Sunar, G. Gaubatz, E. Savas, Sequential circuit design for embedded cryptographic applications resilient to adversarial faults. IEEE Trans. Comput. 57(1), 126–138 (2008)MathSciNetCrossRefGoogle Scholar
  14. 14.
  15. 15.
  16. 16.
    M. Tehranipoor, F. Koushanfar, A survey of hardware Trojan taxonomy and detection. IEEE Des. Test Comput. 27(1), 10–25 (2010)CrossRefGoogle Scholar
  17. 17.
    M. Tehranipoor, C. Wang, Introduction to Hardware Security and Trust (Springer Science & Business Media, New York, 2011)Google Scholar
  18. 18.
    B. Yuce, N.F. Ghalaty, P. Schaumont, TVVF: estimating the vulnerability of hardware cryptosystems against timing violation attacks, in 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (IEEE, Piscataway, 2015), pp. 72–77CrossRefGoogle Scholar
  19. 19.
    B. Yuce, N.F. Ghalaty, C. Deshpande, C. Patrick, L. Nazhandali, P. Schaumont, Fame: fault-attack aware microprocessor extensions for hardware fault detection and software fault response, in Proceedings of the Hardware and Architectural Support for Security and Privacy 2016 (ACM, New York, 2016), p. 8Google Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Farimah Farahmandi
    • 1
  • Yuanwen Huang
    • 2
  • Prabhat Mishra
    • 1
  1. 1.University of FloridaGainesvilleUSA
  2. 2.GoogleMountain ViewUSA

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