VLSI Implementation of K-Best MIMO Detector with Cost-Effective Pre-screening and Fast Sorting Design
For MIMO detections, the K-Best algorithm has been widely applied for multiple-antenna wireless communications. In this paper, to raise the throughput by the cost-effective architecture, the efficient pre-screening and fast sorting schemes are used for the proposed K-Best detector. At first, the pre-screening based enumeration decreases almost half number of leaf nodes for searching, and the searching number of leaf nodes is reduced by the pre-screening based scheme. Next, the applied fast sorting method reduces the hardware complexity in the sorting process. For VLSI realization, the developed MIMO detector is implemented by TSMC 90 nm CMOS technology. The throughput of proposed 4 × 4 K-Best detector achieves up to 4.4 Gbps at the 64QAM mode. Compared with previous K-Best hardware designs, the proposed design provides larger throughputs and performs higher hardware efficiency.
This work was supported by the Ministry of Science and Technology, Taiwan (R.O.C.). The authors thank the National Chip Implementation Center in Taiwan for EDA supports.
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