A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

  • Chirag Sudarshan
  • Jan LappasEmail author
  • Christian Weis
  • Deepak M. Mathew
  • Matthias Jung
  • Norbert Wehn
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11733)


Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting heterogeneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33 mW at a frequency of 500 MHz and has a total area of 4.71 mm2 for UMC 65 nm process.


DRAM DDR3 Memory controller Transprecision PHY 



The project OPRECOMP acknowledges the financial support of the Future and Emerging Technologies (FET) programme within the European Unions Horizon 2020 research and innovation programme, under grant agreement No. 732631 ( This work was also supported by the Fraunhofer High Performance Center for Simulation- and Software-based Innovation.


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Chirag Sudarshan
    • 1
  • Jan Lappas
    • 1
    Email author
  • Christian Weis
    • 1
  • Deepak M. Mathew
    • 1
  • Matthias Jung
    • 2
  • Norbert Wehn
    • 1
  1. 1.Technische Universität KaiserslauternKaiserslauternGermany
  2. 2.Fraunhofer Institute for Experimental Software Engineering (IESE)KaiserslauternGermany

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