Energy-Efficient ARM64 Cluster with Cryptanalytic Applications

Thom Wiggers

doi:10.1007/978-3-030-25283-0_10

International Conference on Cryptology and Information Security in Latin America

LATINCRYPT 2017: Progress in Cryptology – LATINCRYPT 2017 pp 175-188 | Cite as

Energy-Efficient ARM64 Cluster with Cryptanalytic Applications

80 Cores That Do Not Cost You an ARM and a Leg

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Authors and affiliations

Thom Wiggers

Conference paper

First Online: 20 July 2019

Part of the Lecture Notes in Computer Science book series (LNCS, volume 11368)

Abstract

Getting a lot of CPU power used to be an expensive undertaking. Servers with many cores cost a lot of money and consume large amounts of energy. The developments in hardware for mobile devices has resulted in a surge in relatively cheap, powerful, and low-energy CPUs. In this paper we show how to build a low-energy, eighty-core cluster built around twenty ODROID-C2 development boards for under 1500 USD. The ODROID-C2 is a 46 USD microcomputer that provides a 1.536 GHz quad-core Cortex-A53-based CPU and 2 GB of RAM. We investigate the cluster’s application to cryptanalysis by implementing Pollard’s Rho method to tackle the Certicom ECC2K-130 elliptic curve challenge. We optimise software from the Breaking ECC2K-130 technical report for the Cortex-A53. To do so, we show how to use microbenchmarking to derive the needed instruction characteristics which ARM neglected to document for the public. The implementation of the ECC2K-130 attack finally allows us to compare the proposed platform to various other platforms, including “classical” desktop CPUs, GPUs and FPGAs. Although it may still be slower than for example FPGAs, our cluster still provides a lot of value for money.

Keywords

ARM Compute cluster Cryptanalysis Elliptic curve cryptography ECC2K-130

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A Cortex-A53 Benchmarking Results

In this section we will provide an overview of our results with microbenchmarking. As described in Sect. 3.1 we measured the execution times of various instructions. We also looked at various combinations of instructions to learn about pipelining behaviour and execution units.

A.1 Operations On “Normal” Registers

Our findings for AArch64 instructions are shown in Table 6. When measuring two arithmetic instructions we noticed that they take the time as a single instruction. This suggests that the Cortex-A53 has two ALUs and thus can compute two arithmetic instructions at the same time. This does not hold for multiplication or the memory operations and we suspect that the architecture only has one multiplier and a single processing unit for memory access.

Table 6.

Hypothesised instruction characteristics for instructions operating on registers. Latencies are including the issue cycles. Many instructions can be dual-issued.

Instruction	Mnemonic	Issue cycles	Latency (cycles)
Exclusive Or	eor	1	1
And	and	1	1
Or	orr	1	1
Or Not	orn	1	1
Addition	add	1	1
Subtraction	sub	1	1
Multiplication	mul	2	4
Load	ldr	1	1
Load Pair	ldp	2	first: 2, second: 3
Store	str	1	—
Store Pair	stp	2	—

A.2 Operations On NEON Vector Registers

The NEON vector registers are available in different sizes. It is possible to access them as 64-bit vectors or as 128-bit vectors. Tables 7 and 8 give an overview of our results. For the 64-bit vectors we again notice that two arithmetic instructions run in the same time as a single instruction. This however is not the case with the 128-bit vectors. This suggests that there are two 64-bit execution units that are combined for the 128-bit values.

Load and store operations again do not execute in parallel and we suspect there is only one load-store-unit. It is possible to pair up an arithmetic operation with a load or store.

B The ECC2K-130 Challenge Parameters

The Certicom ECC2K-130 challenge is defined in [11, 12]. The challenge is to find integer k such that $Q=[k]P$ on the Koblitz curve $y^2 + xy = x^3 + 1$ defined over $\mathbb {F}_{2^{131}}$. The group order $|E(\mathbb {F}_{2^{131}})| = 4l$, where l is the 129-bit prime number

$$ l = 680564733841876926932320129493409985129. $$

The coordinates of P and Q are given in a polynomial-basis representation of $F_2[z]/(F)$ where $F(z) = z^{131} + z^{13} + z^{2} + z + 1$. They are represented below as hexadecimal bit strings with respect to this basis.

$$\begin{aligned} P_x&= \mathtt {05 1C99BFA6 F18DE467 C80C23B9 8C7994AA} \\ P_y&= \mathtt {04 2EA2D112 ECEC71FC F7E000D7 EFC978BD} \\ Q_x&= \mathtt {06 C997F3E7 F2C66A4A 5D2FDA13 756A37B1} \\ Q_y&= \mathtt {04 A38D1182 9D32D347 BD0C0F58 4D546E9A} \\ \end{aligned}$$

Table 7.

Hypothesised instruction characteristics for instructions operating on 64-bit vectors. Latencies are including the issue cycles. Arithmetic operations can be issued together with other arithmetic instructions or with a load or store operation.

Instruction	Mnemonic	Issue cycles	Latency (cycles)
Exclusive Or	eor	1	1
And	and	1	1
Or	orr	1	1
Or Not	orn	1	1
Addition	add	1	2
Subtraction	sub	1	2
Multiplication	mul	1	4
Load	ldr	2	2
Load Pair	ldp	4	first: 3, second: 4
Store	str	2	—
Store Pair	stp	4	—

Table 8.

Hypothesised instruction characteristics for instructions operating on 128-bit vectors. Latencies are including the issue cycles.

Instruction	Mnemonic	Issue cycles	Latency (cycles)
Exclusive Or	eor	1	1
And	and	1	1
Or	orr	1	1
Or Not	orn	1	1
Addition	add	1	2
Subtraction	sub	1	2
Multiplication	mul	1	4
Load	ldr	2	3
Load Pair	ldp	4	first: 4, second: 5
Store	str	2	—
Store Pair	stp	4	—

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Thom Wiggers
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1.Institute of Computing and Information ScienceRadboud UniversityNijmegenThe Netherlands

Energy-Efficient ARM64 Cluster with Cryptanalytic Applications

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