Advertisement

Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems

  • Md Adnan Zaman
  • Rajeev Joshi
  • Srinivas KatkooriEmail author
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 561)

Abstract

For NOR-NOT based memristor crossbar architectures, we propose a novel approach to address the fanout overhead problem. Instead of copying the logic value as inputs to the driven memristors, we propose that the controller reads the logic value and then applies it in parallel to the driven memristors. We consider two different cases based on the initialization of the memristors to logic-1 at the locations where we want keep the first input memristor of the driven gates. If the memristors are initialized, it falls under case 1, otherwise case 2. In comparison to recently published works, experimental evaluation on ISCAS’85 benchmarks resulted in average performance improvements of 51.08%, 38.66%, and 63.18% for case 1 and 50.94%, 42.08%, and 60.65% for case 2 considering three different mapping scenarios (average, best, and worst). In regards to energy dissipation, we have also obtained average improvements of 91.30%, 88.53%, and 74.04% for case 1 and 86.03%, 78.97%, and 51.89% for case 2 considering the aforementioned scenarios.

Keywords

Memristor In-memory computing Fanout MAGIC Crossbar Logic synthesis Resistive memory 

References

  1. 1.
    Wulf, W.A., McKee, S.A.: Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput. Arch. News 23(1), 20–24 (1995)CrossRefGoogle Scholar
  2. 2.
    Hur, R.B., Kvatinsky, S.: Memristive memory processing unit (MPU) controller for in-memory processing. In: 2016 IEEE International Conference on the Science of Electrical Engineering (ICSEE), pp. 1–5, November 2016Google Scholar
  3. 3.
    Kvatinsky, S., Friedman, E.G., Kolodny, A., Weiser, U.C.: The desired memristor for circuit designers. IEEE Circuits Syst. Mag. 12(2), 17–22 (2013). SecondquarterCrossRefGoogle Scholar
  4. 4.
    Lehtonen, E., Poikonen, J.H., Laiho, M.: Memristive stateful logic. In: Adamatzky, A., Chua, L. (eds.) Memristor Networks, pp. 603–623. Springer, Cham (2014).  https://doi.org/10.1007/978-3-319-02630-5_27CrossRefGoogle Scholar
  5. 5.
    Talati, N., Gupta, S., Mane, P., Kvatinsky, S.: Logic design within memristive memories using memristor-aided loGIC (MAGIC). IEEE Trans. Nanotechnol. 15(4), 635–650 (2016)CrossRefGoogle Scholar
  6. 6.
    Nair, R.: Evolution of Memory Architecture. Proc. IEEE 103(8), 1331–1345 (2015)CrossRefGoogle Scholar
  7. 7.
    Hur, R.B., Wald, N., Talati, N., Kvatinsky, S.: Simple magic: synthesis and in-memory mapping of logic execution for memristor-aided logic. In: 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 225–232, November 2017Google Scholar
  8. 8.
    Gharpinde, R., Thangkhiew, P.L., Datta, K., Sengupta, I.: A scalable in-memory logic synthesis approach using memristor crossbar. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(2), 355–366 (2018)CrossRefGoogle Scholar
  9. 9.
    Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 90215. http://www.eecs.berkeley.edu/~alanmi/abc/
  10. 10.
    Zaman, M.A., Katkoori, S.: Minimizing performance and energy overheads due to fanout in memristor based logic implementations. In: 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 7–12, October 2018Google Scholar
  11. 11.
    Chua, L.: Memristor-The missing circuit element. IEEE Trans. Circuit Theory 18(5), 507–519 (1971)CrossRefGoogle Scholar
  12. 12.
    Strukov, D.B., Snider, G.S., Stewart, D.R., Williams, R.S.: The missing memristor found. Nature 453(7191), 80–83 (2008)CrossRefGoogle Scholar
  13. 13.
    Ali, A.H., Hur, R.B., Wald, N., Kvatinsky, S.: Efficient algorithms for in-memory fixed point multiplication using MAGIC. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, May 2018Google Scholar
  14. 14.
    Kvatinsky, S., Ramadan, M., Friedman, E.G., Kolodny, A.: VTEAM: a general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II: Express Briefs 62(8), 786–790 (2015)CrossRefGoogle Scholar
  15. 15.
    Talati, N., et al.: Practical challenges in delivering the promises of real processing-in-memory machines. In: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1628–1633, March 2018Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2019

Authors and Affiliations

  • Md Adnan Zaman
    • 1
  • Rajeev Joshi
    • 1
  • Srinivas Katkoori
    • 1
    Email author
  1. 1.Department of Computer Science and EngineeringUniversity of South FloridaTampaUSA

Personalised recommendations