VLSI Logic Design and HDL

  • Veena S. Chakravarthi


This chapter discusses different VLSI design techniques highlighting coding style for synthesis. It covers important design concepts like synchronous and asynchronous circuits, clock and reset circuits, clock domain crossovers, speed matching, and so on. In addition, it deals with behavioral modelling, structural modelling, standard cell libraries, and different file formats generated during design phases with SOC design context. The reader is advised to refer VLSI logic design books (A Verilog HDL primer, J Bhaskar; VHDL primer Jayaram Bhaskar, A System Verilog primer, J Bhaskar) for fundamental understanding of VLSI design and books on hardware description languages like Verilog and VHDL for clear understanding and mastering them.


Synchronous design Asynchronous design Sequential circuits Combinational circuits Asynchronous reset Synchronous reset Clock domain crossover HDL Verilog VHDL FSMs Hard macro Soft macro Modelling styles 


  1. 1.
    A Verilog HDL primer, J BhaskarGoogle Scholar
  2. 2.
    VHDL primer Jayaram BhaskarGoogle Scholar
  3. 3.
    A System Verilog primer, J BhaskarGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Veena S. Chakravarthi
    • 1
  1. 1.Sensesemi Technologies Private LimitedBangaloreIndia

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