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Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators

  • Johanna RohdeEmail author
  • Lukas Johannes Jung
  • Christian Hochberger
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11444)

Abstract

Configurable hardware accelerators offer the opportunity to execute compute intense parts of applications with a higher performance and a higher energy efficiency as in pure software execution. One important component in such accelerators is the memory access to the system memory. Typically, this is realized through a cache hierarchy. In this contribution, we implement two different cache coherence protocols in two different configurable HW accelerators on real hardware. Using multiple benchmarks, we evaluate the influence of the cache coherence protocol on the execution time of the accelerators. As a result, we show that the Dragon protocol performs better than the MOESI protocol.

References

  1. 1.
    Archibald, J., Baer, J.L.: Cache coherence protocols: evaluation using a multiprocessor simulation model. ACM Trans. Comput. Syst. 4, 273–298 (1986)CrossRefGoogle Scholar
  2. 2.
    Choi, J., Nam, K., Canis, A., Anderson, J., Brown, S., Czajkowski, T.: Impact of cache architecture and interface on performance and area of FPGA-based processor/parallel-accelerator systems. In: FCCM 2012, April 2012Google Scholar
  3. 3.
    Cong, J., Huang, H., Ma, C., Xiao, B., Zhou, P.: A fully pipelined and dynamically composable architecture of CGRA. In: FCCM 2014, May 2014Google Scholar
  4. 4.
    Hempel, G., Hochberger, C.: A resource optimized processor core for FPGA based SoCs. In: 10th Euromicro DSD Conference on Architectures, Methods and Tools, August 2007Google Scholar
  5. 5.
    Hempel, G., Hochberger, C., Raitza, M.: Towards GCC-based automatic soft-core customization. In: 22nd International Conference on Field Programmable Logic and Applications (FPL), August 2012Google Scholar
  6. 6.
    Hoy, C., et al.: Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation. In: 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, PA, pp. 203–214 (2015).  https://doi.org/10.1109/ISPASS.2015.7095806
  7. 7.
    Paulino, N.M.C., Ferreira, J.C., Cardoso, J.M.P.: Trace-based reconfigurable acceleration with data cache and external memory support. In: 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications, August 2014Google Scholar
  8. 8.
    Prabhakar, R., et al.: Plasticine: a reconfigurable architecture for parallel patterns. In: Proceedings of the 44th ISCA, ISCA 2017. ACM (2017)Google Scholar
  9. 9.
    Rohde, J., Hochberger, C.: Using GCC analysis techniques to enable parallel memory accesses in HLS. In: Fourth International Workshop on FPGAs for Software Programmers, FSP 2017, September 2017Google Scholar
  10. 10.
    Ruschke, T., Jung, L.J., Wolf, D., Hochberger, C.: Scheduler for inhomogeneous and irregular CGRAs with support for complex control flow. In: 2016 IPDPSW, May 2016Google Scholar
  11. 11.
    Solihin, Y.: Fundamentals of Parallel Multicore Architecture. Chapman and Hall/CRC, Boca Raton (2015)CrossRefGoogle Scholar
  12. 12.
    Vijaykrishnan, N., Ranganathan, N.: Supporting object accesses in a Java processor. IEE Proc. Comput. Digital Tech. 147(6), 435–443 (2000)CrossRefGoogle Scholar
  13. 13.
    Winterstein, F., Fleming, K., Yang, H., Wickerson, J., Constantinides, G.: Custom-sized caches in application-specific memory hierarchies. In: 2015 International Conference on Field Programmable Technology (FPT), December 2015Google Scholar
  14. 14.
    Wolf, D.L., Jung, L.J., Ruschke, T., Li, C., Hochberger, C.: AMIDAR project: lessons learned in 15 years of researching adaptive processors. In: 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), July 2018Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of Electrical Engineering and Information Technology, Computer Systems GroupTU DarmstadtDarmstadtGermany

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