A Novel Design and Implementation of 8-Bit and 16-Bit Hybrid ALU

  • Suhas B. ShirolEmail author
  • S. Ramakrishna
  • Rajashekar B. Shettar
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 940)


Arithmetic Logic Unit (ALU) are main constructing block of several digital computation systems like digital calculator, mobile phone, high computational computer, Digital signal processors etc. In current scenario electronic market as technology is raising every day, Fast rising technologies with handy devices demands for low power VLSI design. Ultimatum design with less delay, low power and low area is increasing. Reversible logic gates are suitable to minimize the power dissipation in the circuit, designed reversible logic is suitable. ALU design is intended with both reversible logic gates and irreversible logic gates to reduce dissipation, switching power and delay. The proposed type of design are said to be Hybrid ALU architecture. In arithmetical adder, time taken to propagate carry are minimized by using KSA and CSA, BEC is used to minimize area instead of Ripple Carry Adder. Adder design are utilized to add partial products in Vedic-multiplier, which minimizes delay in digital multiplier.


Arithmetic Logic Unit (ALU) Carry Select Adder (CSA) Kogge-Stone Adder (KSA) Binary to Execs one Converter (BEC) Ripple Carry Adder (RCA) Hybrid ALU 


  1. 1.
    Nautiyal, P., Madduri, P., Negi, S.: Implementation of an ALU using modified carry select adder for low power and area-efficient applications. In: 2015 International Conference on Computer and Computational Sciences (ICCCS), pp. 22–25. IEEE (2015)Google Scholar
  2. 2.
    Sudeep, M., Vucha, M., et al.: Design and FPGA implementation of high speed vedic multiplier. Int. J. Comput. Appl. 90(16) (2014)Google Scholar
  3. 3.
    Shirol, S., Ramakrishna, S., Shettar, R.: A novel design and implementation of 32-bit hybrid ALU. In: Second International Research Symposium on Computing and Network Sustainability (IRSCNS 2018) (2018)Google Scholar
  4. 4.
    Swamynathan, S., Banumathi, V.: Design and analysis of FPGA based 32 bit ALU using reversible gates. In: 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE), pp. 1–4. IEEE (2017)Google Scholar
  5. 5.
    Gokhale, G., Gokhale, S.: Design of area and delay efficient vedic multiplier using carry select adder. In: 2015 International Conference on Information Processing (ICIP), pp. 295–300. IEEE (2015)Google Scholar
  6. 6.
    Elangadi, S., Shirol, S.: Design and characterization of high speed carry select adder. Int. J. Ethics Eng. Manag. Educ. 1(6), 35–40 July 2014Google Scholar
  7. 7.
    Banerjee, A., Das, D.K.: A new ALU architecture design using reversible logic. In: 2016 Sixth International Symposium on Embedded Computing and System Design (ISED), pp. 187–191. IEEE (2016)Google Scholar
  8. 8.
    Pattnaik, S.K., Nanda, U., Nayak, D., Mohapatra, S.R., Nayak, A.B., Mallick, A.: Design and implementation of different types of full adders in ALU and leakage minimization. In: 2017 International Conference on Trends in Electronics and Informatics (ICEI), pp. 924–927. IEEE (2017)Google Scholar
  9. 9.
    Shirol, S., Ramakrishna, S., Shettar, R.: Design and implementation of adders and multiplier in FPGA using Chipscope: a performance improvement. In: Information and Communication Technology for Competitive Strategies. Lecture Notes in Networks and Systems. Scholar
  10. 10.
    Saha, P., Banerjee, A., Bhattacharyya, P., Dandapat, A.: High speed ASIC design of complex multiplier using vedic mathematics. IEEE (2011)Google Scholar
  11. 11.
    Ramkumar, B., Kittur, H.M.: Low-power and area-efficient carry select adder. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(2), 371–375 February 2012CrossRefGoogle Scholar
  12. 12.
    Jais, A., Palsodkar, P.: SM-IEEE: Design and Implementation of 64 Bit Multiplier using Vedic Algorithm, 6–8 April 2016. IEEE (2016)Google Scholar
  13. 13.
    Kandasamy, N., Telagam, N., Devisupraja, C.: Design of a low-power ALU and synchronous counter using clock gating technique. In: Saeed, K., Chaki, N., Pati, B., Bakshi, S., Mohapatra, D. (eds.) Progress in Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol. 564. Springer, Singapore (2018)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Suhas B. Shirol
    • 1
    Email author
  • S. Ramakrishna
    • 1
  • Rajashekar B. Shettar
    • 1
  1. 1.Department of Electronics and Communication EngineeringB V Bhoomaraddi College of Engineering and TechnologyHubballiIndia

Personalised recommendations