60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
The work on low-power TX front-ends started from an initial design (Khalaf in 2013 IEEE 13th topical meeting on silicon monolithic integrated circuits in RF systems (SiRF), 6–8, [Khalaf13]) that can be used for benchmarking. The reference design includes a transformer-coupled three-stage balanced class-A PA stages and a current-bleeding Gilbert-cell upconversion mixer. The chip (see Fig. 3.1) is implemented in 40nm-LP CMOS technology and achieves a P1dB of 9.3 dBm and a Gp of 26 dB. The TX front-end consumes 160mW from a 1.1V supply with maximum and 5 dB back-off PA PAE of 13% and 2%, respectively, and occupies an area of \(220\,\times \, 90\,\upmu \)m2.