Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications

  • Vivek NautiyalEmail author
  • Lalit Gupta
  • Gaurav Singla
  • Jitendra Dasani
  • Sagar Dwivedi
  • Martin Kinkade
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 500)


The purpose of the Power-on Reset (POR) circuit is to reset the latches and flip-flops in an SOC to a known state when the supply is ramping up. During power-up, supply is not stable, and the ramp-up time can vary depending on the applications. A common approach is to generate a POR signal by comparing the supply voltage with a reference voltage. Pseudo dual/two port memories are used in graphic applications where parallel computing is prime factor instead of performance. IoT applications comprise significant image and video processing for which these memories are used. Conventional SRAM does not need a POR circuit but pseudo dual/two port memory face functionality issues without a POR circuit. Low-power applications, like Internet of Things (IoT) devices, comprise of SRAM arrays, sensors, and logic operating at sub-threshold or extremely low voltages. Conventional POR circuits also use a resistor divider circuit along with band gap reference. At these low operating voltages, generating a stable reference voltage is difficult because of band gap reference limitations and process variations. In this paper, we present multiple POR circuits that operates without using a reference voltage, making it robust against different sources of variation. First proposed circuit is self-timed, meaning the reset signal pulse-width varies according to the time needed to reset the latch. The designed circuit has been fabricated in 16 nm FinFET technology. Silicon validation shows that the proposed POR circuit works at a minimum supply voltage of 400 mv. Simulation verifies that the POR circuit is operational in sub-threshold region but is limited to 400 mV on silicon due to the operational voltage of additional testchip logic. Also, the POR circuit does not consume any dynamic power during normal operation of the SOC and has minimal area overhead of 21.3 µm2. Second proposed circuit is latch based self-feedback circuit which resolves limitations of the initial proposed circuit.


Power-on Reset (POR) Sub-threshold 16 nm FinFET Self timed, Internet of Things (IoT) 


  1. 1.
    Nautiyal, V., et al.: Robust, self-timed power-on reset circuit for low-voltage applications. In: 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE (2017)Google Scholar
  2. 2.
    Gupta, L., et al.: Power-on-reset circuit. U.S. Patent Application No. 15/143,197Google Scholar
  3. 3.
    Shen, S.N.: Power-on reset pulse generator. U.S. Patent No. 4,591,745, 27 May 1986Google Scholar
  4. 4.
    Hanke, C.C., Obregon, C.D., Sutton, T.W.: CMOS power-on reset circuit. U.S. Patent No. 4,970,408, 13 November 1990Google Scholar
  5. 5.
    Guo, J., et al.: Power-on-reset circuit with power-off auto-discharging path for passive RFID tag ICs. In: 2010 53rd IEEE International Midwest Symposium on Circuits and Systems. IEEE (2010)Google Scholar
  6. 6.
    Giuffredi, L., et al.: A programmable power-on-reset circuit for automotive applications. In: 2015 11th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME). IEEE (2015)Google Scholar
  7. 7.
    Yasuda, T.R., Yamamoto, M., Nishi, T.: A power-on reset pulse generator for low voltage applications. In: The 2001 IEEE International Symposium on Circuits and Systems 2001, ISCAS 2001, vol. 4. IEEE (2001)Google Scholar
  8. 8.
    Burdia, D., et al.: Power-on reset circuit for SoC with multiple I/O power supplies. In: 2011 10th International Symposium on Signals, Circuits and Systems (ISSCS). IEEE (2011)Google Scholar
  9. 9.
    Chhabra, A., Vaderiya, Y.D.: Low-energy power-on-reset circuit for dual supply SRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(5), 2003–2007 (2016)CrossRefGoogle Scholar
  10. 10.
    Zhang, J., Jiang, L., Zeng, Z.: Design of a novel power-on-reset circuit based on power supply detector. In: International Conference on Scalable Computing and Communications; Eighth International Conference on Embedded Computing 2009, SCALCOM-EMBEDDEDCOM 2009. IEEE (2009)Google Scholar
  11. 11.
    Yen, W.-C., Chen, H.-W., Lin, Y.-T.: A precision CMOS power-on-reset circuit with power noise immunity for low-voltage technology. IEICE Trans. Electron. 87(5), 778–784 (2004)Google Scholar
  12. 12.
    Katyal, A., Bansal, N.: A self-biased current source-based power-on reset circuit for on-chip applications. In: 2006 International Symposium on VLSI Design, Automation and Test. IEEE (2006)Google Scholar
  13. 13.
    Prakash, R.: Zero quiescent current delay adjustable power-on-reset circuit. In: Circuits and Systems Conference (DCAS) 2014. IEEE, Dallas (2014)Google Scholar
  14. 14.
    Nautiyal, V., et al.: An ultra-high-density pseudo dual-port SRAM in 16 nm FINFET process for graphics processors. In: 2017 30th International Symposium on System-on-Chip Conference (SOCC). IEEE (2017)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2019

Authors and Affiliations

  • Vivek Nautiyal
    • 1
    Email author
  • Lalit Gupta
    • 1
  • Gaurav Singla
    • 1
  • Jitendra Dasani
    • 1
  • Sagar Dwivedi
    • 1
  • Martin Kinkade
    • 1
  1. 1.ARM Inc.San JoseUSA

Personalised recommendations