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Analysis of Efficiency and THD in 7-Level Voltage Inverters with Reduced Number of Switches

  • Ales HavelEmail author
  • Martin Sobek
  • Petr Chamrad
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 554)

Abstract

This paper focuses on analyzes of theoretical efficiencies and total harmonic distortions of modern topologies of 7-level voltage inverters with reduced number of switches. Three different topologies of 7-level voltage inverters controlled with subharmonic PWM methods were built and analyzed in the Matlab/Simulink environment. The results are focused mainly on determining the THD of the output phase voltage and total power losses of the presented topologies. These parameters are used to determine the optimal circuit topology and modulation technique for control of the 7-level voltage inverter.

Keywords

7- level voltage inverter Efficiency Reduced number of switches Subharmonic PWM Total harmonic distortion Total power losses 

Notes

Acknowledgment

This paper was supported by the projects: Center for Intelligent Drives and Advanced Machine Control (CIDAM) project, Reg. No. TE02000103 funded by the Technology Agency of the Czech Republic and Project Reg. No. SP2018/162 funded by the Student Grant Competition of VSB – Technical University of Ostrava.

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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.VSB - Technical University of OstravaOstrava-PorubaCzech Republic

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