IP Generator Tool for Efficient Hardware Acceleration of Self-organizing Maps

  • Daniele Giardino
  • Marco Matta
  • Marco Re
  • Francesca Silvestri
  • Sergio SpanòEmail author
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 573)


In this paper, authors present an IP generator for FPGA-based hardware acceleration of Kohonen’s Self-Organizing Maps (SOM). The IP generator is realized in MATLAB and offers the user the possibility to design an efficient FPGA hardware accelerator with several settings such as the number of features and the number of neurons. The optimization is achieved by applying some approximations to the original SOM algorithm, these modifications do not affect the functionality of the map. The generated IP cores can be used both for training and inference and the software can check the clustering performances.


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Daniele Giardino
    • 1
  • Marco Matta
    • 1
  • Marco Re
    • 1
  • Francesca Silvestri
    • 1
  • Sergio Spanò
    • 1
    Email author
  1. 1.University of Rome Tor VergataRomeItaly

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