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IP Generator Tool for Efficient Hardware Acceleration of Self-organizing Maps

  • Daniele Giardino
  • Marco Matta
  • Marco Re
  • Francesca Silvestri
  • Sergio SpanòEmail author
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 573)

Abstract

In this paper, authors present an IP generator for FPGA-based hardware acceleration of Kohonen’s Self-Organizing Maps (SOM). The IP generator is realized in MATLAB and offers the user the possibility to design an efficient FPGA hardware accelerator with several settings such as the number of features and the number of neurons. The optimization is achieved by applying some approximations to the original SOM algorithm, these modifications do not affect the functionality of the map. The generated IP cores can be used both for training and inference and the software can check the clustering performances.

References

  1. 1.
    Lo Sciuto, G., Susi, G., Cammarata, G., Capizzi, G.: A spiking neural network-based model for anaerobic digestion process. In: IEEE 23rd International Symposium on Power Electronics, Electrical Drives, Automation and Motion (2016)Google Scholar
  2. 2.
    Brusca, S., Capizzi, G., Lo Sciuto, G., Susi, G.: A new design methodology to predict wind farm energy production by means of a spiking neural network based-system. Int. J. Numer. Model. Electron. Netw. Devices Fields 7 (2017)Google Scholar
  3. 3.
    Scarpato, N., Pieroni, A., Di Nunzio, L., Re, M., Salerno, M., Susi, G.: E-health-IoT universe: A review. Int. J. Adv. Sci. Eng. Inf. Technol. 7(6), 2328–2336 (2017)CrossRefGoogle Scholar
  4. 4.
    Cardarilli, G.C., Cristini, A., Di Nunzio, L., Re, M., Salerno, M., Susi, G.: Spiking neural networks based on LIF with latency: simulation and synchronization effects. In: Asilomar Conference on Signals, Systems and Computers (2016)Google Scholar
  5. 5.
    Khanal, G.M., Acciarito, S., Cardarilli, G.C., Chakraborty, A., Di Nunzio, L., Fazzolari, R., Cristini, A., Re, M., Susi, G.: Synaptic behaviour in ZnO-rGO composites thin film memristor. Electron. Lett. 53(5), 296–298 (2017)CrossRefGoogle Scholar
  6. 6.
    Acciarito, S., Cardarilli, G.C., Cristini, A., Di Nunzio, L., Fazzolari, R., Khanal, G.M., Re, M., Susi, G.: Hardware design of LIF with Latency neuron model with memristive STDP synapses. Integr. VLSI J. 59, 81–89 (2017)CrossRefGoogle Scholar
  7. 7.
    Khanal, G.M., Cardarilli, G., Chakraborty, A., Acciarito, S., Mulla, M.Y., Di Nunzio, L., Fazzolari, R., Re, M.: A ZnO-rGO composite thin film discrete memristor. IEEE, ICSE, Article No. 7573608, pp. 129–132 (2016)Google Scholar
  8. 8.
    Acciarito, S., Cristini, A., Di Nunzio, L., Khanal, G.M., Susi, G.: An a VLSI driving circuit for memristor-based STDP. PRIME 2016, Article No. 7519503 (2016)Google Scholar
  9. 9.
    Giuliano, R., Mazzenga, F., Neri, A., Vegni, A.M.: Security access protocols in IoT capillary networks. IEEE Internet Things J. 4(3), 645–657 (2017)CrossRefGoogle Scholar
  10. 10.
    Sacchi C., Rossi T., Menapace M., Granelli F.: Utilization of UWB transmission techniques for broadband satellite connections operating in W-Band. In: 2008 IEEE Globecom Workshops (2008) 1–6Google Scholar
  11. 11.
    Dalmasso I., Galletti I., Giuliano R., Mazzenga F.: WiMAX networks for emergency management based on UAVs. In: IEEE—AESS European Conference on Satellite Telecommunications, pp. 1–6 (2012)Google Scholar
  12. 12.
    Kohonen, T.: The self-organizing map. Neurocomputing 21, 1–6 (1998)CrossRefGoogle Scholar
  13. 13.
    Martín-del-Brío, B., Blasco-Alberto, J.: Hardware-oriented models for VLSI implementation of self-organizing maps. In: International Workshop on Artificial Neural Networks, pp. 712–719 (1995)Google Scholar
  14. 14.
    Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Re, M., Silvestri, F., Spanò, S.: Energy consumption saving in embedded microprocessors using hardware accelerators. Telkomnika 16(3), 1019–1026 (2018)CrossRefGoogle Scholar
  15. 15.
    Cardarilli, G.C., Di Nunzio, L., Fazzolari, R., Re, M., Lee, R.B.: Integration of butterfly and inverse butterfly nets in embedded processors: effects on power saving. In: Conference Record - Asilomar Conference on Signals, Systems and Computers, Article No. 6489268, pp. 1457–1459 (2012)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Daniele Giardino
    • 1
  • Marco Matta
    • 1
  • Marco Re
    • 1
  • Francesca Silvestri
    • 1
  • Sergio Spanò
    • 1
    Email author
  1. 1.University of Rome Tor VergataRomeItaly

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