An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding

  • Paolo Selvo
  • Maurizio Masera
  • Riccardo Peloso
  • Guido Masera
  • Muhammad Shafique
  • Maurizio MartinaEmail author
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 573)


Sum of Absolute Differences (SAD) is one of the most time consuming tasks in video coding. This paper proposes an architecture to compute the SADs for all the different block sizes required by the High Efficiency Video Coding (HEVC) standard. Moreover, the Partial Distortion Elimination (PDE), clock gating and a low leakage technology enable high power/energy reductions/savings over the state of the art.


VLSI architecture Motion estimation HEVC 


  1. 1.
    Bossen, F., Bross, B., Suhring, K., Flynn, D.: HEVC complexity and implementation analysis. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1685–1696 (2012)CrossRefGoogle Scholar
  2. 2.
    Chiu, M.Y., Siu, W.C.: New results on exhaustive search algorithm for motion estimation using adaptive partial distortion search and successive elimination algorithm. In: 2006 IEEE International Symposium on Circuits and Systems, pp. 4–3981 (May 2006)Google Scholar
  3. 3.
    Dinh, V.N., Phuong, H.A., Duc, D.V., Ha, P.T.K., Tien, P.V., Thang, N.V.: High speed SAD architecture for variable block size motion estimation in HEVC encoder. In: 2016 IEEE International Conference on Communications and Electronics, pp. 195–198 (July 2016)Google Scholar
  4. 4.
    El-Harouni, W., Rehman, S., Prabakaran, B.S., Kumar, A., Hafiz, R., Shafique, M.: Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding. In: Design, Automation and Test in Europe Conference, pp. 1384–1389 (Mar 2017)Google Scholar
  5. 5.
    Medhat, A., Shalaby, A., Sayed, M.S.: High-throughput hardware implementation for motion estimation in HEVC encoder. In: IEEE International Midwest Symposium on Circuits and Systems, pp. 1–4 (Aug 2015)Google Scholar
  6. 6.
    Medhat, A., Shalaby, A., Sayed, M.S., Elsabrouty, M., Mehdipour, F.: A highly parallel SAD architecture for motion estimation in HEVC encoder. In: IEEE Asia Pacific Conference on Circuits and Systems, pp. 280–283 (Nov 2014)Google Scholar
  7. 7.
    Nalluri, P., Alves, L.N., Navarro, A.: High speed SAD architectures for variable block size motion estimation in HEVC video coding. In: IEEE International Conference on Image Processing, pp. 1233–1237 (Oct 2014)Google Scholar
  8. 8.
    Seidel, I., Brascher, A.B., Guntzel, J.L.: Combining pel decimation with partial distortion elimination to increase SAD energy efficiency. In: International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 177–184 (Sept 2015)Google Scholar
  9. 9.
    Selvo, P.: VHDL code of an optimized SAD architecture for HEVC (Oct 2017).
  10. 10.
    Sullivan, G.J., Ohm, J.R., Han, W.J., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1649–1668 (2012)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Paolo Selvo
    • 1
  • Maurizio Masera
    • 1
  • Riccardo Peloso
    • 1
  • Guido Masera
    • 1
  • Muhammad Shafique
    • 2
  • Maurizio Martina
    • 1
    Email author
  1. 1.Department of Electronics and TelecommunicationsPolitecnico di TorinoTurinItaly
  2. 2.Institute of Computer EngineeringVienna University of Technology (TU Wien)ViennaAustria

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