Advertisement

Design of Low-Power Approximate LMS Filters with Precision-Scalability

  • Darjn EspositoEmail author
  • Gennaro Di Meo
  • Davide De Caro
  • Antonio G. M. Strollo
  • Ettore Napoli
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 573)

Abstract

Approximate Computing (AC) waives error free computation to improve circuits performances. Adaptive Least-Mean-Squares (LMS) filters can benefit from AC, being both power hungry and inherently approximate. In this paper an approximate LMS filter is proposed, which is able to change, at runtime, the precision level by acting on an external quality knob. An auxiliary circuit enables the approximation mode, in which the update of some of the filter coefficients is frozen. The proposed filter achieves a power improvement in the range 5–32%, as function of the tolerable quality degradation.

References

  1. 1.
    Han, J., Orshansky, M.: Approximate computing: An emerging paradigm for energy-efficient design. In: 18th IEEE European Test Symp. (ETS), Avignon, pp. 1–6 (2013)Google Scholar
  2. 2.
    Roy, K., Raghunathan, A.: Approximate computing: an energy-efficient computing technique for error resilient applications. In: IEEE Computer Society Annual Symposium VLSI, pp. 473–475 (2015)Google Scholar
  3. 3.
    Shafique, M., Ahmad, W., Hafiz, R.: A low latency generic accuracy configurable adder. In: DAC Design Automation Conference, San Francisco, CA, pp. 1–6 (2015)Google Scholar
  4. 4.
    Esposito, D., Castellano, G., De Caro, D., Napoli, E., Petra, N., Strollo, A.G.M.: Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, pp. 1970–1973 (2016)Google Scholar
  5. 5.
    Verma, A.K., Brisk, P., Ienne, P.: Variable latency speculative addition: a new paradigm for arithmetic circuit design. In: Proceedings of Design, Automation and Test in Europe, Munich, pp. 1250–1255 (2008)Google Scholar
  6. 6.
    Esposito, D., De Caro, D., Napoli, E., Petra, N., Strollo, A.G.M.: Variable latency speculative han-carlson adder. IEEE Trans. Circuits Syst. I Regul. Pap. 62(5), 1353–1361 (2015)CrossRefGoogle Scholar
  7. 7.
    Esposito, D., De Caro, D., Strollo, A.G.M.: Variable latency speculative parallel prefix adders for unsigned and signed operands. IEEE Trans. Circuits Syst. I Regul. Pap. 63(8), 1200–1209 (2016)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Esposito, D., Strollo, A.G.M., Napoli, E., De Caro, D., Petra, N.: Approximate multipliers based on new approximate compressors. IEEE Trans. Circuits Syst. I Regul. Pap.  https://doi.org/10.1109/tcsi.2018.2839266CrossRefGoogle Scholar
  9. 9.
    Haykin, S.: Adaptive Filter Theory. Prentice-Hall (2002)Google Scholar
  10. 10.
    Meher, P.K., Park, S.Y.: Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm. IEEE Trans. Circuits and Syst. I 61(3), 778–788 (2014)CrossRefGoogle Scholar
  11. 11.
    Esposito, D., Di Meo, G., De Caro, D., Petra, N., Napoli, E., Strollo, A.G.M.: On the use of approximate multipliers in LMS adaptive filters. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, pp. 1–5 (2018)Google Scholar
  12. 12.
    Frustaci, F., Khayatzadeh, M., Blaauw, D., Sylvester, D., Alioto, M.: SRAM for error-tolerant applications with dynamic energy-quality management in 28 nm CMOS. IEEE J. Solid State Circuits 50(5), 1310–1323 (2015)CrossRefGoogle Scholar
  13. 13.
    Esposito, D., Strollo, A.G.M., Alioto, M.: Power-precision scalable latch memories. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, pp. 1–4 (2017)Google Scholar
  14. 14.
    de la Guia Solaz, M., Han, W., Conway, R.: A flexible low power DSP with a programmable truncated multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 59(11), 2555–2568 (2012)MathSciNetCrossRefGoogle Scholar
  15. 15.
    Moons, B., Verhelst, M.: An energy-efficient precision-scalable ConvNet processor in 40-nm CMOS. IEEE J. Solid State Circuits 52(4), 903–914 (2017)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Darjn Esposito
    • 1
    Email author
  • Gennaro Di Meo
    • 1
  • Davide De Caro
    • 1
  • Antonio G. M. Strollo
    • 1
  • Ettore Napoli
    • 1
  1. 1.Department of Electrical Engineering and Information TechnologyUniversity of Napoli “Federico II”NaplesItaly

Personalised recommendations