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A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis

  • Nereo Markulic
  • Kuba Raczkowski
  • Jan Craninckx
  • Piet Wambacq
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

This chapter introduces an analog fractional-N subsampling PLL that relies on a digital-to-time (DTC) converter in the phase-error comparison path for fractional residue compensation. Since the DTC is put at the input of the system, its resolution, linearity, and phase noise performance introduce the bottleneck for the overall spectral purity. A high-efficiency, low-noise 10-bit DTC with 0.5 ps resolution is designed. Analog sensitivities of the circuit (such as DTC gain variation) are compensated in the digital domain. The prototype achieves a robust fractional lock across the range from 9.2 GHz to 12.7 GHz with less than 280-fs rms integrated jitter (in presence of the worst fractional spur). The total power consumption of the PLL is 13 mW.

References

  1. [Auvergne00]
    D. Auvergne, J.M. Daga, M. Rezzoug, Signal transition time effect on CMOS delay evaluation. IEEE Trans. Circuits Syst. I: Fund. Theory Appl. 47(9), 1362–1369 (2000)CrossRefGoogle Scholar
  2. [Borremans10]
    J. Borremans, K. Vengattaramane, V. Giannini, J. Craninckx, A 86 MHz-to-12 GHz digital-intensive phase-modulated fractional-N PLL using a 15 pJ/Shot 5 ps TDC in 40 nm digital CMOS, in 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). (IEEE, San Francisco, 2010), pp. 480–481Google Scholar
  3. [Chang14]
    W.-S. Chang, P.-C. Huang, T.-C. Lee, A fractional-N divider-less phase-locked loop with a subsampling phase detector. IEEE J. Solid State Circuits 49(12), 2964–2975 (2014)CrossRefGoogle Scholar
  4. [Chillara14]
    V.K. Chillara, Y.-H. Liu, B. Wang, A. Ba, M. Vidojkovic, K. Philips, H. de Groot, R.B. Staszewski, 9.8 An 860 μW 2.1-to-2.7 GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). (IEEE, San Francisco, 2014), pp. 172–173Google Scholar
  5. [Gao09a]
    X. Gao, E. Klumperink, P. Geraedts, B. Nauta, Jitter analysis and a benchmarking figure-of-merit for phase-locked loops. IEEE Trans. Circuits Syst. Express Briefs 56(2), 117–121 (2009)CrossRefGoogle Scholar
  6. [Gao09b]
    X. Gao, E. Klumperink, M. Bohsali, B. Nauta, A Low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N 2. IEEE J. Solid State Circuits 44(12), 3253–3263 (2009)CrossRefGoogle Scholar
  7. [Gao10]
    X. Gao, E. Klumperink, G. Socci, M. Bohsali, B. Nauta, Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector. IEEE J. Solid State Circuits 45(9), 1809–1821 (2010)CrossRefGoogle Scholar
  8. [Hershberg14]
    B. Hershberg, K. Raczkowski, K. Vaesen, J. Craninckx, A 9.1–12.7 GHz VCO in 28 nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction, in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC). (IEEE, Venice Lido, 2014), pp. 83–86Google Scholar
  9. [Levantino04]
    S. Levantino, L. Romanò, S. Pellerano, C. Samori, A. Lacaita, Phase noise in digital frequency dividers. IEEE J. Solid State Circuits 39(5), 775–784 (2004)CrossRefGoogle Scholar
  10. [Levantino13]
    S. Levantino, G. Marzin, C. Samori, A. Lacaita, A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration. IEEE J. Solid State Circuits 48(10), 2419–2429 (2013) [Online]. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6576220 CrossRefGoogle Scholar
  11. [Markulic14]
    N. Markulic, K. Raczkowski, P. Wambacq, J. Craninckx, A 10-bit, 550-fs step Digital-to-Time Converter in 28 nm CMOS, in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC). (IEEE, Venice Lido, 2014), pp. 79–82Google Scholar
  12. [Marucci14]
    G. Marucci, A. Fenaroli, G. Marzin, S. Levantino, C. Samori, A.L. Lacaita, 21.1 A 1.7 GHz MDLL-based fractional-N frequency synthesizer with 1.4 ps RMS integrated jitter and 3 mW power using a 1b TDC, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). (IEEE, San Francisco, 2014), pp. 360–361Google Scholar
  13. [Marucci15]
    G. Marucci, Techniques for high-efficiency digital frequency synthesis. PhD Thesis, Politecnico di Milano, Italy, 2015Google Scholar
  14. [Marzin12]
    G. Marzin, S. Levantino, C. Samori, A.L. Lacaita, “A 20 Mb/s phase modulator based on a 3.6 GHz digital PLL with − 36 dB EVM at 5 mW power. IEEE J. Solid State Circuits 47(12), 2974–2988 (2012)CrossRefGoogle Scholar
  15. [Marzin14]
    G. Marzin, S. Levantino, C. Samori, A.L. Lacaita, 2.9 A background calibration technique to control bandwidth in digital PLLs, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). (IEEE, San Francisco, 2014), pp. 54–55Google Scholar
  16. [Pavlovic11]
    N. Pavlovic, J. Bergervoet, A 5.3 GHz digital-to-time-converter-based fractional-N all-digital PLL, in 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). (IEEE, San Francisco, 2011), pp. 54–56Google Scholar
  17. [Raczkowski15]
    K. Raczkowski, N. Markulic, B. Hershberg, J. Craninckx, A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28 nm CMOS with 280 fs RMS jitter. IEEE J. Solid State Circuits 50(5), 1203–1213 (2015)CrossRefGoogle Scholar
  18. [Riley93]
    T.A. Riley, M.A. Copeland, T.A. Kwasniewski, Delta-sigma modulation in fractional-N frequency synthesis. IEEE J. Solid State Circuits 28(5), 553–559 (1993)CrossRefGoogle Scholar
  19. [Ru15]
    J.Z. Ru, C. Palattella, P. Geraedts, E. Klumperink, B. Nauta, A high-linearity digital-to-time converter technique: constant-slope charging. IEEE J. Solid State Circuits 50(6), 1412–1423 (2015)CrossRefGoogle Scholar
  20. [Schreier05]
    R. Schreier, G.C. Temes, Understanding Delta-Sigma Data Converters, vol. 74. (IEEE Press, Piscataway, 2005)Google Scholar
  21. [Sjoland02]
    H. Sjoland, Improved switched tuning of differential CMOS VCOs. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process. 49(5), 352–355 (2002)CrossRefGoogle Scholar
  22. [Staszewski04]
    R.B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J.L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung et al, All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid State Circuits 39(12), 2278–2291 (2004)CrossRefGoogle Scholar
  23. [Swaminatha07]
    A. Swaminathan, K. Wang, I. Galton, A wide-bandwidth 2.4 GHz ISM band fractional-N PLL with adaptive phase noise cancellation. IEEE J. Solid State Circuits 42(12), 2639–2650 (2007)CrossRefGoogle Scholar
  24. [Szortyka14]
    V. Szortyka, Q. Shi, K. Raczkowski, B. Parvais, M. Kuijk, P. Wambacq, 21.4 A 42 mW 230 fs-jitter sub-sampling 60 GHz PLL in 40 nm CMOS, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). (IEEE, San Francisco, 2014), pp. 366–367 [Online]. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6757472
  25. [Tasca11]
    D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, A. Lacaita, A 2.9–4.0-GHz fractional-N digital PLL with bang-bang phase detector and 560-fs RMS integrated jitter at 4.5-mW power. IEEE J. Solid State Circuits 46(12), 2745–2758 (2011)CrossRefGoogle Scholar
  26. [Temporiti10]
    E. Temporiti, C. Weltin-Wu, D. Baldi, M. Cusmai, F. Svelto, A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. IEEE J. Solid State Circuits 45(12), 2723–2736 (2010)Google Scholar
  27. [Vaucher00]
    C. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology. IEEE J. Solid State Circuits 35(7), 1039–1045 (2000) [Online]. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=848214 CrossRefGoogle Scholar
  28. [Yang06]
    Y.-C. Yang, S.-A. Yu, Y.-H. Liu, T. Wang, S.-S. Lu, A Quantization noise suppression technique for Δ Σ fractional-N frequency synthesizers. IEEE J. Solid State Circuits 41(11), 2500–2511 (2006)CrossRefGoogle Scholar
  29. [Yao11]
    C.-W. Yao, L. Lin, B. Nissim, H. Arora, T. Cho, A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 ps RMS jitter, in 2011 Symposium on VLSI Circuits - Digest of Technical Papers. (IEEE, Honolulu, 2011), pp. 110–111Google Scholar
  30. [Zhuang12]
    J. Zhuang, R.B. Staszewski, A low-power all-digital PLL architecture based on phase prediction, in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS). (IEEE, Seville, 2012), pp. 797–800Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Nereo Markulic
    • 1
  • Kuba Raczkowski
    • 1
  • Jan Craninckx
    • 1
  • Piet Wambacq
    • 1
  1. 1.IMECLeuvenBelgium

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