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Residue Logarithmic Coprocessor for Mass Arithmetic Computations

  • Ilya OsininEmail author
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 965)

Abstract

The work is aimed at solving the urgent problems of modern high-performance computing. The purpose of the study is to increase the speed, accuracy and reliability of mass arithmetic calculations. To achieve the goal, author’s methods of performing operations and transforming data in the prospective residue logarithmic number system are used. This numbering system makes it possible to unite the advantages of non-conventional number systems: a residue number system and a logarithmic number system. The subject of study is a parallel-pipelined coprocessor implementing the proposed calculation methods. The study was carried out using the theory of computer design and systems, methods and means of experimental analysis of computers and systems. As a result of the research and development new scientific and technical solutions are proposed that implement the proposed methods of data computation and coding. The proposed coprocessor has high speed, accuracy and reliability of processing of real operands in comparison with known analogs based on the floating-point positioning system.

Keywords

Logarithmic number system Residue number system Residue logarithmic number system Performance Accuracy Reliability 

References

  1. 1.
    754-2008 – IEEE Standard for floating-Point Arithmetic. Revision of ANSI/IEEE Std 754-1985. http://ieeexplore.ieee.org. Accessed 12 Apr 2018
  2. 2.
    Arnold, M.G.: The residue logarithmic number system: theory and implementation. In: 17th IEEE Symposium on Computer Arithmetic, pp. 196–205 (2002)Google Scholar
  3. 3.
    Chervyakov, N.I.: Modular Parallel Computing Structures of Neuroprocessor Systems. Fizmatlit Publishers, Moscow (2003)Google Scholar
  4. 4.
    Knyazkov, V.S., Isupov, K.S.: Parallell multiple-precision arithmetic based on residue number system. Program Syst. Theor. Appl. 7(28), 61–97 (2016)Google Scholar
  5. 5.
    Garner, H.: Number Systems and Arithmetic. In: Advances in Computers, vol. 6, pp. 131–194 (1966)Google Scholar
  6. 6.
    Omondi, A.: Residue Number System: Theory and Implementation. Imperial College Press, London (2007)CrossRefGoogle Scholar
  7. 7.
    Osinin, I.P.: The organization of a parallel-pipelined VLSI-processor for direct conversion of numbers based on the arithmetic of the bit-slices. In: News of higher Educational Institutions, Technical Science, The Volga Region, vol. 4, pp. 5–13 (2014)Google Scholar
  8. 8.
    Isupov, K.S.: Algorithms for estimating modular numbers in floating-point arithmetic. In: Science Innovation and Technologies, vol. 4, pp. 44–56 (2016)Google Scholar
  9. 9.
    Coleman, J.N., Chester, E.I., Softley, C.I., Kadlec, J.: Arithmetic on the European logarithmic microprocessor. IEEE Trans. Comput. 49, 702–715 (2000).  https://doi.org/10.1109/12.863040CrossRefGoogle Scholar
  10. 10.
    Arnold, M., Bailey, T., Cowles, J., Winkel, M.: Arithmetic co-transformations in the real and complex logarithmic number systems. IEEE Trans. Comput. 47, 777–786 (1998).  https://doi.org/10.1109/12.709377MathSciNetCrossRefzbMATHGoogle Scholar
  11. 11.
    Coleman, J.N.: Simplification of table structure in logarithmic arithmetic. Electron. Lett. 31, 1905–1906 (1995).  https://doi.org/10.1049/el:19951304CrossRefGoogle Scholar
  12. 12.
    Lewis, D.M.: An architecture for addition and subtraction of long word length numbers in the logarithmic number system. IEEE Trans. Comput. 39, 1325–1336 (1990).  https://doi.org/10.1109/12.61042CrossRefGoogle Scholar
  13. 13.
    Osinin, I.P.: Optimization of the hardware costs of interpolation converters for calculations in the logarithmic number system. In: Proceedings of the International Scientific Conference Parallel Computational Technologies (PCT 2018), pp. 153–164 (2018)Google Scholar
  14. 14.
    Osinin, I.P.: Method and device of parallel-pipelined arithmetical computers in modular-logarithmic system. Eurasian Union Sci. 3(48), 45–56 (2018)Google Scholar
  15. 15.
    Osinin, I.P.: Method and device of direct parallel-pipelined transformation of numbers with floating point in modular-logarithmic format. Eurasian Union Sci. 3(48), 56–69 (2018)Google Scholar
  16. 16.
    Osinin, I.P.: Method and device for the backward parallel-pipelined transformation of modular-logarithmic numbers in a format with a floating point. Eurasian Union Sci. 3(48), 70–83 (2018)Google Scholar
  17. 17.
    Osinin, I.P.: A modular-logarithmic coprocessor concept. In: Proceedings International Conference on High Performance Computing and Simulation (HPCS-2017), pp. 588–595 (2017).  https://doi.org/10.1109/hpcs.2017.93
  18. 18.
    Intel 64 and IA-32 Architectures Optimization Reference Manual. http://www.intel.com. Accessed 12 Apr 2018

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Limited Liability Company Scientific Production Association Real-Time Software ComplexesMoscowRussia

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