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Design of Heterogeneous Evaluation Method for Redundant Circuits

  • Huicong Wu
  • Jie Yu
  • Yangang Wang
  • Xiaoguang Wang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11344)

Abstract

Fault-tolerant mechanisms have been an essential part of the electronic equipment in extreme environments such as high voltage, extreme temperature and strong electromagnetic environment etc. Accordingly, how to improve the robustness and disturbance rejection performance of the circuit has become the primary problem in recent years. In this paper, a heterogeneous evaluation method based on relational analysis is proposed. It uses genetic algorithm and evolutionary hardware to get the required sub-circuit structures and uses relational strategy to evaluate heterogeneous degree of redundant circuit system. Finally, the sub-structures with large heterogeneous degree are selected to build redundant circuit system. In the experiments, we designed short-circuit fault and parameter drift fault to validate the heterogeneous evaluation method. The experimental results show this method can not only enhance the heterogeneous degree, but also maintain high robustness. Compared with random heterogeneous redundant system and homogeneous redundant system, the Average Fault-free Probability of redundant fault-tolerant circuit system based on relational method is 8.9% and 21.7% higher respectively in short-circuit fault experiments, and it is 9.1% and 23.9% higher respectively in parameter drift fault experiments.

Keywords

Fault-tolerance Redundancy Algorithm Heterogeneous evaluation method Relational strategy 

Notes

Acknowledgments

This work was partly supported by the National Key R&D Program of China (No. 2017YFB0202202), the State Key Program of National Natural Science Foundation of China (No. 91530324).

References

  1. 1.
    Liu, S.F., Cai, H., Yang, Y.J.: Advance in grey incidence analysis modelling. Syst. Eng. Theory Pract. 33(8), 2041–2046 (2013)Google Scholar
  2. 2.
    Liu, Z., Dang, Y.G., Zhou, W.J.: New grey nearness incidence model and its extension. Control. Decis. 29(6), 1071–1075 (2014)zbMATHGoogle Scholar
  3. 3.
    Chen, Y.M., Zhang, M.: Cubic spline based grey absolute relational grade model. Syst. Eng. Theory Pract. 35(5), 1304–1310 (2015)Google Scholar
  4. 4.
    Jiang, S.Q., Liu, S.F., Liu, Z.X.: Grey incidence decision making model based on area. Control Decis. 30(4), 685–690 (2015)Google Scholar
  5. 5.
    Zhang, M., He, J.: Vector analysis on the fault-tolerant abilities of combined analog circuit systems. In: proceeding of International Congress on Image and Signal Processing, Biomedical Engineering and Informatics, pp. 2020–2025 (2017)Google Scholar
  6. 6.
    Chang, H., He, J.: A novel fault-tolerance design model for automatic synthesis of circuit robust to unknown fault. In: Proceeding of Conference Anthology, pp. 1–6. IEEE (2014)Google Scholar
  7. 7.
    Chang, H., He, J.: Swarm intelligence: making differences in analogue circuits structure for fault-tolerance. Int. J. Comput. Appl. Technol. 46(3), 210–219 (2013)CrossRefGoogle Scholar
  8. 8.
    Zheng, Y., He, J.: Learning the distance between circuit structures for fault tolerance of redundant system. In: proceeding of Seventh International Symposium on Computational Intelligence and Design, pp. 207–211 (2015)Google Scholar
  9. 9.
    Chen, Z., Ni, M.: Reliability and security analysis of triple-module redundancy system. Comput. Eng. 38(14), 239–241 (2012)Google Scholar
  10. 10.
    Gao, G.J., Wang, Y.R., Yao, R.: Research on redundancy and tolerance of system with different structures. Transducer Microsyst. Technol. 26(10), 25–28 (2007)Google Scholar
  11. 11.
    Shi, W., Yuan, L., Xie, S.J.: Research on selective redundancy of evolved circuits using negative correlation. Microelectron Comput. 30(6), 71–74 (2013)Google Scholar
  12. 12.
    Wu, H.C., Wang, J.Z., Liu, C.C.: Research of circuit evolution design based on adaptive HereBoy algorithm. J. Hebei Univ. Sci. Technol. 36(3), 293–299 (2015)Google Scholar
  13. 13.
    Liu, M., He, J.: An evolutionary negative-correlation framework for robust analog-circuit design under uncertain faults. IEEE Trans. Evol. Comput. 17(5), 640–665 (2013)CrossRefGoogle Scholar
  14. 14.
    Wu, H.C., Wang, J.Z., Zhou, W.Z.: Redundancy fault-tolerant circuit design based on feature map clustering and heterogeneous selection strategy. High Volt. Eng. 43(4), 1362–1369 (2017)Google Scholar
  15. 15.
    Zhang, J.B., Cai, J.Y., Meng, Y.F.: A design technology of fault tolerance circuit systems facing complex electromagnetic environments. J. Xi’an Jiaotong Univ. 51(2), 53–59 (2017)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  • Huicong Wu
    • 1
  • Jie Yu
    • 1
  • Yangang Wang
    • 2
  • Xiaoguang Wang
    • 2
  1. 1.College of Information Science and EngineeringHebei University of Science and TechnologyShijiazhuangChina
  2. 2.Computer Network Information Center, Chinese Academy of SciencesBeijingChina

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